ARMv7 "write buffer" issue

Note: This was originally posted on 3rd July 2012 at http://forums.arm.com

Hi All,

I have a question about the "write buffer" for ARMv7 processor.

Write buffer is explicitly described in TRM(tech reference manual) prior to ARMv6. E.g, how to enable/disable it, how to configure it in a MMU page table descriptor etc.

However, it looks to me that write buffer is not explicitly described in TRM of ARMv7. So I have some questsions below. Could someone confirm if my understanding is correct.

For ARMv7 processor:

1. Write buffer is only used by "Normal" memory , "strongly-ordered" and "device" memory have nothing do do with it. Is this correct?
2. For the normal memory, despite the cacheability configuration, write buffer will always be used? Is this correct?

Thanks in advance.
-Jerry
Parents
  • Note: This was originally posted on 3rd July 2012 at http://forums.arm.com

    Write buffer is only used by "Normal" memory , "strongly-ordered" and "device" memory have nothing do do with it. Is this correct?


    Normal and device memory can both be buffered in the write buffer. Device memory accesses cannot be reordered or merged in the write buffer, normal memory can be.

    2. For the normal memory, despite the cacheability configuration, write buffer will always be used? Is this correct?


    Define what a "write buffer" actually is? Really all it means is that writes are held internally and even though the load instruction has retired it may not be visible on the external memory interface yet. In that light you could really view the cache as a very large write buffer for cached memory.
    For interest, why do you actually care? The presence of a write buffer is merely an optimization, and as long as you follow the architecture requirements for cache flushes and/or memory barriers you won't have to worry about it.
Reply
  • Note: This was originally posted on 3rd July 2012 at http://forums.arm.com

    Write buffer is only used by "Normal" memory , "strongly-ordered" and "device" memory have nothing do do with it. Is this correct?


    Normal and device memory can both be buffered in the write buffer. Device memory accesses cannot be reordered or merged in the write buffer, normal memory can be.

    2. For the normal memory, despite the cacheability configuration, write buffer will always be used? Is this correct?


    Define what a "write buffer" actually is? Really all it means is that writes are held internally and even though the load instruction has retired it may not be visible on the external memory interface yet. In that light you could really view the cache as a very large write buffer for cached memory.
    For interest, why do you actually care? The presence of a write buffer is merely an optimization, and as long as you follow the architecture requirements for cache flushes and/or memory barriers you won't have to worry about it.
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