• State Not Answered
  • Locked Locked
  • Replies 4 replies
  • Subscribers 346 subscribers
  • Views 6021 views
  • Users 0 members are here
Options
Related
How was your experience today?
This discussion has been locked.
You can no longer post new replies to this discussion. If you have a question you can start a new discussion

ARMv7 "write buffer" issue

Zhanguo Li
Note: This was originally posted on 3rd July 2012 at http://forums.arm.com

Hi All,

I have a question about the "write buffer" for ARMv7 processor.

Write buffer is explicitly described in TRM(tech reference manual) prior to ARMv6. E.g, how to enable/disable it, how to configure it in a MMU page table descriptor etc.

However, it looks to me that write buffer is not explicitly described in TRM of ARMv7. So I have some questsions below. Could someone confirm if my understanding is correct.

For ARMv7 processor:

1. Write buffer is only used by "Normal" memory , "strongly-ordered" and "device" memory have nothing do do with it. Is this correct?
2. For the normal memory, despite the cacheability configuration, write buffer will always be used? Is this correct?

Thanks in advance.
-Jerry
  • 0
    Note: This was originally posted on 4th July 2012 at http://forums.arm.com

    Thanks ttfn.

    Hi isogen74,

    You gave me very helpful answer. Thanks.



    Define what a "write buffer" actually is? Really all it means is that writes are held internally and even though the load instruction has retired it may not be visible on the external memory interface yet. In that light you could really view the cache as a very large write buffer for cached memory. 

    I understand. And this time, what I foucus on is the small write buffer after the cache.



    For  interest, why do you actually care? The presence of a write buffer is  merely an optimization, and as long as you follow the architecture  requirements for cache flushes and/or memory barriers you won't have to  worry about it.


    Well, we are developing some CortexA9 multi-core BSPs for different hardware vendors.  For L1 cache, DSB is enough to use as the memory barriers as "drain write buffer" is also done with this instructions. However, for the extern L2 cache(with PL310/330controller), we need another explicit "drain buffer" operation in drivers. We've resolved the problems and I just want to know more informaion in ARMv7.

    Thanks.
  • 0
    Note: This was originally posted on 3rd July 2012 at http://forums.arm.com

    Write buffer is only used by "Normal" memory , "strongly-ordered" and "device" memory have nothing do do with it. Is this correct?


    Normal and device memory can both be buffered in the write buffer. Device memory accesses cannot be reordered or merged in the write buffer, normal memory can be.

    2. For the normal memory, despite the cacheability configuration, write buffer will always be used? Is this correct?


    Define what a "write buffer" actually is? Really all it means is that writes are held internally and even though the load instruction has retired it may not be visible on the external memory interface yet. In that light you could really view the cache as a very large write buffer for cached memory.
    For interest, why do you actually care? The presence of a write buffer is merely an optimization, and as long as you follow the architecture requirements for cache flushes and/or memory barriers you won't have to worry about it.
  • 0
    Note: This was originally posted on 3rd July 2012 at http://forums.arm.com

    AFAIK marking an address range as Device/Strongly ordered only prevents caching, speculation and adds ordering constraints.  Architecturally buffering of writes is allowed to any memory type.  (Which is different from saying that a particular processor _will_ buffer, just that it would be allowed to do so).

    If you need the write to have happened you need a DSB.