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<?xml-stylesheet type="text/xsl" href="https://community.arm.com/utility/feedstylesheets/rss.xsl" media="screen"?><rss version="2.0" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:slash="http://purl.org/rss/1.0/modules/slash/" xmlns:wfw="http://wellformedweb.org/CommentAPI/"><channel><title>Strange behaviour of cache</title><link>https://community.arm.com/developer/tools-software/tools/f/armds-forum/947/strange-behaviour-of-cache</link><description> Note: This was originally posted on 19th November 2011 at http://forums.arm.com Hi! I have a Cortex a9 based board (currently only 1core is active another one is waiting for its time to come into a play). My simplified caching routine in pseudo code</description><dc:language>en-US</dc:language><generator>Telligent Community 10</generator><item><title>RE: Strange behaviour of cache</title><link>https://community.arm.com/thread/2797?ContentTypeID=1</link><pubDate>Wed, 11 Sep 2013 11:05:18 GMT</pubDate><guid isPermaLink="false">dd9e70c8-6d3c-4c71-b136-2456382a7b5c:0f556f06-7d91-4819-ab9d-bae3983dd198</guid><dc:creator>Zhanguo Li</dc:creator><description>&lt;div&gt;&lt;i&gt;Note: This was originally posted on 22nd November 2011 at &lt;a href="http://forums.arm.com"&gt;http://forums.arm.com&lt;/a&gt;&lt;/i&gt;&lt;br /&gt;&lt;br /&gt;&lt;span&gt;Can you explain more why &amp;quot;It is not possible to separate caching functions from each other&amp;quot;? From my perspective:&lt;/span&gt;&lt;br /&gt;&lt;span&gt;{&lt;/span&gt;&lt;br /&gt;&lt;span&gt;if(cache_op1) {docache_op1(); delay();}&lt;/span&gt;&lt;br /&gt;&lt;span&gt;if(cache_op2)docache_op2();&lt;/span&gt;&lt;br /&gt;&lt;span&gt;}&lt;/span&gt;&lt;br /&gt;&lt;span&gt;It this works fine, then change it to&lt;/span&gt;&lt;br /&gt;&lt;span&gt;{&lt;/span&gt;&lt;br /&gt;&lt;span&gt;if(cache_op1)docache_op1();&lt;/span&gt;&lt;br /&gt;&lt;span&gt;if(cache_op2) {docache_op2(); delay()}&lt;/span&gt;&lt;br /&gt;&lt;span&gt;}&lt;/span&gt;&lt;br /&gt;&lt;span&gt;If this does not work ,then you can know that docache_op2() is probably the reason to cause the problem and then focus on it.&lt;/span&gt;&lt;br /&gt;&lt;br /&gt;&lt;span&gt;It may not be the reason to cause your problem here, but when you perform some operations such as &amp;quot;invalidate/flush/clear all I-Cache D-Cache&amp;quot;, I&amp;#39;d suggest you lock all the interrupts.&lt;/span&gt;&lt;/div&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: Strange behaviour of cache</title><link>https://community.arm.com/thread/2798?ContentTypeID=1</link><pubDate>Wed, 11 Sep 2013 11:05:18 GMT</pubDate><guid isPermaLink="false">dd9e70c8-6d3c-4c71-b136-2456382a7b5c:d314603b-aa28-412f-949b-796ff58b77fe</guid><dc:creator>Jerry Fan</dc:creator><description>&lt;div&gt;&lt;i&gt;Note: This was originally posted on 19th November 2011 at &lt;a href="http://forums.arm.com"&gt;http://forums.arm.com&lt;/a&gt;&lt;/i&gt;&lt;br /&gt;&lt;br /&gt;&lt;span&gt;HI SJS,&lt;/span&gt;&lt;br /&gt;&lt;br /&gt;&lt;span&gt;Maybe you can remove the delay at the end of the function and add delay to the cache_ops to see which cache op result the issue. Such as&amp;#160; &lt;/span&gt;&lt;br /&gt;&lt;span&gt; [color=#222222][size=2]if(cache_op2){ docache_op2(); delay()}[/size][/color]&lt;/span&gt;&lt;br /&gt;&lt;span&gt;[color=#222222][size=2]Please try add some nops to then end of the docache_ops, such as[/size][/color]&lt;/span&gt;&lt;br /&gt;&lt;span&gt;[color=#222222][size=2] [/size][/color][color=#222222][size=2]mov r0, #0[/size][/color][color=#222222][size=2] mcr p15, 0, r0, c7, c5, 0 ; I cache [/size][/color]&lt;/span&gt;&lt;br /&gt;&lt;span&gt;[color=#222222][size=2] mcr p15, 0, r0, c7, c5, 6 ; BP[/size][/color]&lt;/span&gt;&lt;br /&gt;&lt;span&gt;[color=#222222][size=2] DSB[/size][/color]&lt;/span&gt;&lt;br /&gt;&lt;span&gt;[color=#222222][size=2] ISB[/size][/color]&lt;/span&gt;&lt;br /&gt;&lt;span&gt;&amp;#160;&amp;#160; nop&lt;/span&gt;&lt;br /&gt;&lt;span&gt;&amp;#160;&amp;#160; nop&lt;/span&gt;&lt;br /&gt;&lt;span&gt;&amp;#160;&amp;#160; nop&lt;/span&gt;&lt;br /&gt;&lt;span&gt;[color=#222222][size=2] bx lr[/size][/color]&lt;/span&gt;&lt;br /&gt;&lt;span&gt;[color=#222222][size=2]to clean the pipeline.[/size][/color]&lt;/span&gt;&lt;/div&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: Strange behaviour of cache</title><link>https://community.arm.com/thread/2795?ContentTypeID=1</link><pubDate>Wed, 11 Sep 2013 11:05:18 GMT</pubDate><guid isPermaLink="false">dd9e70c8-6d3c-4c71-b136-2456382a7b5c:b8b628be-8a2f-4711-828b-3f89a1d1c661</guid><dc:creator>qwerty ytrewq</dc:creator><description>&lt;div&gt;&lt;i&gt;Note: This was originally posted on 21st November 2011 at &lt;a href="http://forums.arm.com"&gt;http://forums.arm.com&lt;/a&gt;&lt;/i&gt;&lt;br /&gt;&lt;br /&gt;&lt;blockquote&gt;&lt;br /&gt;HI SJS,&lt;br /&gt;&lt;br /&gt;Maybe you can remove the delay at the end of the function and add delay to the cache_ops to see which cache op result the issue. Such as&amp;#160; &lt;br /&gt; if(cache_op2){ docache_op2(); delay()}&lt;br /&gt;Please try add some nops to then end of the docache_ops, such as&lt;br /&gt; mov r0, #0 mcr p15, 0, r0, c7, c5, 0 ; I cache &lt;br /&gt; mcr p15, 0, r0, c7, c5, 6 ; BP&lt;br /&gt; DSB&lt;br /&gt; ISB&lt;br /&gt;&amp;#160;&amp;#160; nop&lt;br /&gt;&amp;#160;&amp;#160; nop&lt;br /&gt;&amp;#160;&amp;#160; nop&lt;br /&gt; bx lr&lt;br /&gt;to clean the pipeline.&lt;br /&gt;&lt;/blockquote&gt;&lt;br /&gt;&lt;span&gt;It is not possible to separate caching functions from each other. They are all called very frequently. So for example delay for one of the functions will serve as delay for all other functions. I am clueless what can actually cause all this. Do you have any ideas, even weird ones?&lt;/span&gt;&lt;/div&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item></channel></rss>