Arm Community
Site
Search
User
Site
Search
User
Groups
Arm Research
DesignStart
Education Hub
Graphics and Gaming
High Performance Computing
Innovation
Multimedia
Open Source Software and Platforms
Physical
Processors
Security
System
Software Tools
TrustZone for Armv8-M
中文社区
Blog
Announcements
Artificial Intelligence
Automotive
Healthcare
HPC
Infrastructure
Innovation
Internet of Things
Machine Learning
Mobile
Smart Homes
Wearables
Forums
All developer forums
IP Product forums
Tool & Software forums
Pelion IoT Platform
Support
Open a support case
Documentation
Downloads
Training
Arm Approved program
Arm Design Reviews
Community Help
More
Cancel
Developer Community
Tools and Software
Software Tools
Jump...
Cancel
Software Tools
Arm Development Studio forum
ARMv6: "invalidate D-cache line" instruction doesn't work?
Tools, Software and IDEs blog
Forums
Videos & Files
Help
Jump...
Cancel
New
Replies
4 replies
Subscribers
127 subscribers
Views
2140 views
Users
0 members are here
Related
ARMv6: "invalidate D-cache line" instruction doesn't work?
Offline
Zhanguo Li
over 7 years ago
Note: This was originally posted on 10th November 2011 at http://forums.arm.com
I am trying to test the "invalidate D-cache line" instruction of Freescale imx31/35 processor(ARMv6) and seems that it fails to work.
Below are my test pseudocode:
1. pBuf = malloc(xxx) /* alloc a write-back memory */
2. *(volatile char *)pBuf = 0; /* not cache hit now and not write-allocate, so 0 is written to memory */
3. data = *(volatile char *)pBuf; /* read the date to cache */
4. *(char *)pBuf = 0xaa; /* write 0xaa to cache */
5. invalidate pBuf cache line; /* via mcr or mcrr instruction */
6. data = *(volatile char *)pBuf; /* read it again */
7. data should not be 0xaa, otherwise the invalidate instruction does not work.
Note that my real test code are more strict than the pseudocode, and it works well in ARMv7 platform
So is there knowd issue for ARMv6 "invalidate D-cache line" instruction?
Thanks a lot!
-Jerry
Offline
Zhanguo Li
over 7 years ago
Note: This was originally posted on 17th November 2011 at
http://forums.arm.com
L2 cache is disabled in my platform
Cancel
Up
0
Down
Reply
Cancel
Offline
Zhanguo Li
over 7 years ago
Note: This was originally posted on 22nd November 2011 at
http://forums.arm.com
Thanks for your reply. ttfn.
Actually I do not need a clean operation here as I just want to test invalidate instructions. And furthermore, DSB has been added in my "invalidate D-cache line" routines.
Cancel
Up
0
Down
Reply
Cancel
Offline
Martin Weidmann
over 7 years ago
Note: This was originally posted on 18th November 2011 at
http://forums.arm.com
An invalidate causes the contents of the cache to be thrown away. Which means that any dirty data (changes held in the cache, but not yet memory) are lost!
If you want external memory to be updated you need to do a clean (or clean + invalidate).
Other things to consider are barriers. You may need to add a DSB between the cache command and the read/write of the address. This is to ensure that they happen in order. This is a side effect of a loosely ordered memory system.
Cancel
Up
0
Down
Reply
Cancel
Offline
Jerry Fan
over 7 years ago
Note: This was originally posted on 16th November 2011 at
http://forums.arm.com
Actually, i.MX31/35 use a IP as L2 cache, and it is external cache. MCR command did not affect the L2 cache. So the L2 cache was not invalidated in your case.
Cancel
Up
0
Down
Reply
Cancel
More questions in this forum
By title
By date
By reply count
By view count
By most asked
By votes
By quality
Descending
Ascending
All recent questions
Unread questions
Questions you've participated in
Questions you've asked
Unanswered questions
Answered questions
Questions with suggested answers
Questions with no replies
Suggested Answer
DS52020.0 connection to Musca-A/B boards not working
0
Arm Development Studio
Musca-A
608
views
3
replies
Latest
15 hours ago
by
Ronan Synnott
Suggested Answer
Positioning a function in a Position Independent Executable for ARMV8
0
1987
views
3
replies
Latest
9 days ago
by
Stephen Theobald
Answered
Link a pure binary file to image with scatter file
0
1955
views
3
replies
Latest
9 days ago
by
Ronan Synnott
Answered
Failed to read contents of Internal RAM L1-I_DATA in ARM DS
0
Arm Development Studio
Cache
Debug and Trace Services Layer (DTSL)
4617
views
23
replies
Latest
22 days ago
by
Boon Khai
Suggested Answer
DS-5 connect fail when cortex-r5 is in lock-step mode
0
4222
views
10
replies
Latest
29 days ago
by
Stuart Hirons
>
View all questions in Arm Development Studio forum