Arm Community
Site
Search
User
Site
Search
User
Groups
Arm Research
DesignStart
Education Hub
Graphics and Gaming
High Performance Computing
Innovation
Multimedia
Open Source Software and Platforms
Physical
Processors
Security
System
Software Tools
TrustZone for Armv8-M
中文社区
Blog
Announcements
Artificial Intelligence
Automotive
Healthcare
HPC
Infrastructure
Innovation
Internet of Things
Machine Learning
Mobile
Smart Homes
Wearables
Forums
All developer forums
IP Product forums
Tool & Software forums
Pelion IoT Platform
Support
Open a support case
Documentation
Downloads
Training
Arm Approved program
Arm Design Reviews
Community Help
More
Cancel
Developer Community
Tools and Software
Software Tools
Jump...
Cancel
Software Tools
Arm Development Studio forum
APB confusion
Tools, Software and IDEs blog
Forums
Videos & Files
Help
Jump...
Cancel
New
Replies
2 replies
Subscribers
127 subscribers
Views
3050 views
Users
0 members are here
Related
APB confusion
Offline
Ganesh Kuppan
over 7 years ago
Note: This was originally posted on 1st September 2011 at http://forums.arm.com
Hi,
This may seem a very basic doubt. I have implemented APB peripheral on a Cortex M1 based ACTEL platform. I do 3 memory writes and 2 memory reads from the peripheral. The hardware peripheral takes 30 cycles to complete operation after 3 writes are completed to it. Then I do 2 reads. So, I estimated the whole operation to be completed in around 40-45 cycles. I read the AMBA specification and it says, APB peripherals require 2 cycles (address and data phase) to complete with no wait states. I have implemented AMBA 2.0 protocol, which does not have PREADY. But each Load or Store to the peripheral is taking 40 cycles each and the total goes to around 200 cycles. How is this possible? Am I missing some knowledge about AMBA APB?
As my AHB2APB bridge is encrypted RTL, I cannot verify whether somehow this bridge is adding wait states (it can as it is a AHB slave).
Is the FPGA slow in responding and so AHB2APB is adding wait cycles?
Also, if APB transfers can also be done in 2 cycles, why not use the AHB for the same with one WAIT state?
My cortex M1, AHB2APB bridge and hardware peripheral are all working on same clock of 20MHz.
Would appreciate a detailed response.
Also to add, the counter used is again a APB peripheral . I write a value 1 to it, to start counting. Then writes to the above HW peripheral start. After the whole write/read operation to above peripheral , I again write a 0 to counter to stop . Then I read the stored counter value. Because both the peripherals are APB and share the bridge any issues??
More questions in this forum
By title
By date
By reply count
By view count
By most asked
By votes
By quality
Descending
Ascending
All recent questions
Unread questions
Questions you've participated in
Questions you've asked
Unanswered questions
Answered questions
Questions with suggested answers
Questions with no replies
Suggested Answer
On Cortex-M4F microcontrollers: is fixed point math faster or floating point?
0
3563
views
10
replies
Latest
29 days ago
by
Ronan Synnott
Suggested Answer
Debugging kernel: OS support not working for Linux 5.4
0
Kernel Developers
External Hardware Debug
Debugger
3204
views
5
replies
Latest
1 month ago
by
sgoldschmidt
Suggested Answer
DS-5 bare metal wait error after run "debug"
0
DS-5 Development Studio
Debugging
Arm Compiler 5
Memory
24693
views
14
replies
Latest
1 month ago
by
prasadghole
Suggested Answer
ARM development studio with ARM Juno r2 board
0
Juno Arm Development Platform
Arm Development Studio
Products
Arm Support
3136
views
2
replies
Latest
1 month ago
by
Ronan Synnott
Answered
"Unable to execute remote query (response code 503) " issue
0
3103
views
1
reply
Latest
1 month ago
by
Ronan Synnott
<
>
View all questions in Arm Development Studio forum