A basic question about data bus transfer

Note: This was originally posted on 29th August 2011 at http://forums.arm.com

In AMBA AHB spec2.0 or AHB lite,
for the data bus transfer with byte, there is a table (Active byte lanes for a 32-bit little-endian data bus) as shown in the attachment.
I am kind of confused with it.
1.
For byte transmission, I thought it was fine by just putting the byte data on data[7:0], why do we need different lanes?

2.
For the address offset, where does it come from?
In another words, how can I know which lane is active?

I googled but could not find some answers, it seemed that everyone knew how to deal with it except me.

Can someone give me some advice on those questions?

Thank you very much.
Parents
  • Note: This was originally posted on 3rd September 2011 at http://forums.arm.com

    Thank you very much.
    I got it.
    The low bits of HWADDR is used to identify offset.
    Then, if I want to transfer 8 bits in 32 bits bus in write mode, it will change its lane from time to time.

    However, I thought it is not a good idea to do this.
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  • Note: This was originally posted on 3rd September 2011 at http://forums.arm.com

    Thank you very much.
    I got it.
    The low bits of HWADDR is used to identify offset.
    Then, if I want to transfer 8 bits in 32 bits bus in write mode, it will change its lane from time to time.

    However, I thought it is not a good idea to do this.
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