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<?xml-stylesheet type="text/xsl" href="https://community.arm.com/utility/feedstylesheets/rss.xsl" media="screen"?><rss version="2.0" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:slash="http://purl.org/rss/1.0/modules/slash/" xmlns:wfw="http://wellformedweb.org/CommentAPI/"><channel><title>Problem disabling cache on ARM926ej-s</title><link>https://community.arm.com/developer/tools-software/tools/f/armds-forum/837/problem-disabling-cache-on-arm926ej-s</link><description> </description><dc:language>en-US</dc:language><generator>Telligent Community 10</generator><item><title>RE: Problem disabling cache on ARM926ej-s</title><link>https://community.arm.com/thread/2337?ContentTypeID=1</link><pubDate>Wed, 11 Sep 2013 11:03:08 GMT</pubDate><guid isPermaLink="false">dd9e70c8-6d3c-4c71-b136-2456382a7b5c:f89347ee-cb84-43ca-b541-5827a9fba7e8</guid><dc:creator>Martin Weidmann</dc:creator><description>&lt;div&gt;&lt;i&gt;Note: This was originally posted on 16th March 2011 at &lt;a href="http://forums.arm.com"&gt;http://forums.arm.com&lt;/a&gt;&lt;/i&gt;&lt;br /&gt;&lt;br /&gt;&lt;span&gt;Are you marking memory as write-back cacheable?&amp;#160; If so, you should be cleaning the D cache as well as invalidating it.&lt;/span&gt;&lt;br /&gt;&lt;br /&gt;&lt;span&gt;Is the memory flat mapped?&lt;/span&gt;&lt;/div&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: Problem disabling cache on ARM926ej-s</title><link>https://community.arm.com/thread/2336?ContentTypeID=1</link><pubDate>Wed, 11 Sep 2013 11:03:08 GMT</pubDate><guid isPermaLink="false">dd9e70c8-6d3c-4c71-b136-2456382a7b5c:268295f8-88b4-4ca6-b325-54c1f6114d73</guid><dc:creator>aleksa</dc:creator><description>&lt;div&gt;&lt;i&gt;Note: This was originally posted on 17th March 2011 at &lt;a href="http://forums.arm.com"&gt;http://forums.arm.com&lt;/a&gt;&lt;/i&gt;&lt;br /&gt;&lt;br /&gt;&lt;span&gt;Got it!&lt;/span&gt;&lt;br /&gt;&lt;br /&gt;&lt;span&gt;&amp;quot;bne DisableCache&amp;quot; should be &amp;quot;bne disablecache&amp;quot;&lt;/span&gt;&lt;/div&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: Problem disabling cache on ARM926ej-s</title><link>https://community.arm.com/thread/2335?ContentTypeID=1</link><pubDate>Wed, 11 Sep 2013 11:03:08 GMT</pubDate><guid isPermaLink="false">dd9e70c8-6d3c-4c71-b136-2456382a7b5c:d441fbc7-ea29-45fc-a5fe-258db30290e0</guid><dc:creator>aleksa</dc:creator><description>&lt;div&gt;&lt;i&gt;Note: This was originally posted on 17th March 2011 at &lt;a href="http://forums.arm.com"&gt;http://forums.arm.com&lt;/a&gt;&lt;/i&gt;&lt;br /&gt;&lt;br /&gt;&lt;span&gt;I&amp;#39;ve copied (almost) this from linux, and it still doesn&amp;#39;t work.&lt;/span&gt;&lt;br /&gt;&lt;br /&gt;&lt;code&gt;&lt;br /&gt;&lt;br /&gt;disablecache:&amp;#160;&amp;#160; mrc p15, 0, r15, c7, c14, 3&amp;#160; @ test, clean and invalidate&lt;br /&gt;&amp;#160;&amp;#160;&amp;#160;&amp;#160;&amp;#160;&amp;#160;&amp;#160;&amp;#160;&amp;#160;&amp;#160;&amp;#160;&amp;#160;&amp;#160;&amp;#160;&amp;#160; bne DisableCache&lt;br /&gt;&lt;br /&gt;&amp;#160;&amp;#160;&amp;#160;&amp;#160;&amp;#160;&amp;#160;&amp;#160;&amp;#160;&amp;#160;&amp;#160;&amp;#160;&amp;#160;&amp;#160;&amp;#160;&amp;#160; mov r0,#0&lt;br /&gt;&amp;#160;&amp;#160;&amp;#160;&amp;#160;&amp;#160;&amp;#160;&amp;#160;&amp;#160;&amp;#160;&amp;#160;&amp;#160;&amp;#160;&amp;#160;&amp;#160;&amp;#160; mcr p15, 0, r0, c7, c5, 0&amp;#160;&amp;#160;&amp;#160; @ invalidate I cache&lt;br /&gt;&amp;#160;&amp;#160;&amp;#160;&amp;#160;&amp;#160;&amp;#160;&amp;#160;&amp;#160;&amp;#160;&amp;#160;&amp;#160;&amp;#160;&amp;#160;&amp;#160;&amp;#160; mcr p15, 0, r0, c7, c10, 4&amp;#160;&amp;#160;&amp;#160;&amp;#160;&amp;#160; @ drain write buffer&lt;br /&gt;&lt;br /&gt;&amp;#160;&amp;#160;&amp;#160;&amp;#160;&amp;#160;&amp;#160;&amp;#160;&amp;#160;&amp;#160;&amp;#160;&amp;#160;&amp;#160;&amp;#160;&amp;#160;&amp;#160; mrc p15, 0, r0, c1, c0, 0&amp;#160;&amp;#160;&amp;#160; @ Disable Icache(12), Dcache(2) and MMU(0)&lt;br /&gt;&amp;#160;&amp;#160;&amp;#160;&amp;#160;&amp;#160;&amp;#160;&amp;#160;&amp;#160;&amp;#160;&amp;#160;&amp;#160;&amp;#160;&amp;#160;&amp;#160;&amp;#160; bic r0, r0, #4096&lt;br /&gt;&amp;#160;&amp;#160;&amp;#160;&amp;#160;&amp;#160;&amp;#160;&amp;#160;&amp;#160;&amp;#160;&amp;#160;&amp;#160;&amp;#160;&amp;#160;&amp;#160;&amp;#160; bic r0, r0, #5&lt;br /&gt;&amp;#160;&amp;#160;&amp;#160;&amp;#160;&amp;#160;&amp;#160;&amp;#160;&amp;#160;&amp;#160;&amp;#160;&amp;#160;&amp;#160;&amp;#160;&amp;#160;&amp;#160; mcr p15, 0, r0, c1, c0, 0&lt;br /&gt;&lt;br /&gt;&amp;#160;&amp;#160;&amp;#160;&amp;#160;&amp;#160;&amp;#160;&amp;#160;&amp;#160;&amp;#160;&amp;#160;&amp;#160;&amp;#160;&amp;#160;&amp;#160;&amp;#160; mov pc,lr&lt;br /&gt;&lt;/code&gt;&lt;/div&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: Problem disabling cache on ARM926ej-s</title><link>https://community.arm.com/thread/2334?ContentTypeID=1</link><pubDate>Wed, 11 Sep 2013 11:03:08 GMT</pubDate><guid isPermaLink="false">dd9e70c8-6d3c-4c71-b136-2456382a7b5c:aef86b46-3a2d-4338-83b4-20f119e9d826</guid><dc:creator>aleksa</dc:creator><description>&lt;div&gt;&lt;i&gt;Note: This was originally posted on 17th March 2011 at &lt;a href="http://forums.arm.com"&gt;http://forums.arm.com&lt;/a&gt;&lt;/i&gt;&lt;br /&gt;&lt;br /&gt;&lt;span&gt;Or maybe like this (please answer)&lt;/span&gt;&lt;br /&gt;&lt;br /&gt;&lt;code&gt;&lt;br /&gt;&lt;br /&gt;&lt;br /&gt;&lt;br /&gt;&lt;br /&gt;disablecache:&amp;#160;&amp;#160;&amp;#160; mov r0,#0&amp;#160;&amp;#160;&amp;#160;&amp;#160;&amp;#160;&amp;#160;&amp;#160;&amp;#160;&amp;#160;&amp;#160;&amp;#160;&amp;#160;&amp;#160;&amp;#160;&amp;#160;&amp;#160; @ drain write buffer&lt;br /&gt;&amp;#160;&amp;#160;&amp;#160;&amp;#160;&amp;#160;&amp;#160;&amp;#160;&amp;#160;&amp;#160;&amp;#160; mcr p15, 0, r0, c7, c10, 4&lt;br /&gt;&lt;br /&gt;&amp;#160;&amp;#160;&amp;#160;&amp;#160;&amp;#160;&amp;#160;&amp;#160;&amp;#160;&amp;#160;&amp;#160; mrc p15, 0, r15, c7, c14, 3&amp;#160; @ test, clean and invalidate&lt;br /&gt;&amp;#160;&amp;#160;&amp;#160;&amp;#160;&amp;#160;&amp;#160;&amp;#160;&amp;#160;&amp;#160;&amp;#160; bne disablecache&lt;br /&gt;&lt;br /&gt; @@@@&amp;#160;&amp;#160;&amp;#160;&amp;#160;&amp;#160;&amp;#160;&amp;#160;&amp;#160;&amp;#160;&amp;#160;&amp;#160; mcr p15, 0, r0, c7, c6, 0&amp;#160;&amp;#160;&amp;#160; @ invalidate dcache&lt;br /&gt;&lt;br /&gt;&amp;#160;&amp;#160;&amp;#160;&amp;#160;&amp;#160;&amp;#160;&amp;#160;&amp;#160;&amp;#160;&amp;#160; mrc p15, 0, r0, c1, c0, 0&amp;#160;&amp;#160;&amp;#160; @ Disable Icache(12), Dcache(2) and MMU(0)&lt;br /&gt;&amp;#160;&amp;#160;&amp;#160;&amp;#160;&amp;#160;&amp;#160;&amp;#160;&amp;#160;&amp;#160;&amp;#160; bic r0, r0, #4096&lt;br /&gt;&amp;#160;&amp;#160;&amp;#160;&amp;#160;&amp;#160;&amp;#160;&amp;#160;&amp;#160;&amp;#160;&amp;#160; bic r0, r0, #5&lt;br /&gt;&amp;#160;&amp;#160;&amp;#160;&amp;#160;&amp;#160;&amp;#160;&amp;#160;&amp;#160;&amp;#160;&amp;#160; mcr p15, 0, r0, c1, c0, 0&lt;br /&gt;&lt;br /&gt;&amp;#160;&amp;#160;&amp;#160;&amp;#160;&amp;#160;&amp;#160;&amp;#160;&amp;#160;&amp;#160;&amp;#160; mov pc,lr&amp;#160;&amp;#160;&amp;#160;&amp;#160;&amp;#160;&amp;#160;&amp;#160;&amp;#160;&amp;#160;&amp;#160;&amp;#160;&amp;#160;&amp;#160;&amp;#160;&amp;#160;&amp;#160; @ return to SWI handler&lt;br /&gt;&lt;br /&gt;&lt;br /&gt;&lt;/code&gt;&lt;br /&gt;&lt;br /&gt;&lt;br /&gt;&lt;br /&gt;&lt;br /&gt;&lt;span&gt;What about those NOPs or delays I see in some sources after accessing CP15?&lt;/span&gt;&lt;br /&gt;&lt;br /&gt;&lt;/div&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: Problem disabling cache on ARM926ej-s</title><link>https://community.arm.com/thread/2333?ContentTypeID=1</link><pubDate>Wed, 11 Sep 2013 11:03:08 GMT</pubDate><guid isPermaLink="false">dd9e70c8-6d3c-4c71-b136-2456382a7b5c:47bdded5-99c5-4f44-8e16-71b300ea2d65</guid><dc:creator>aleksa</dc:creator><description>&lt;div&gt;&lt;i&gt;Note: This was originally posted on 16th March 2011 at &lt;a href="http://forums.arm.com"&gt;http://forums.arm.com&lt;/a&gt;&lt;/i&gt;&lt;br /&gt;&lt;br /&gt;&lt;span&gt;&amp;gt; Are you marking memory as write-back cacheable?&lt;/span&gt;&lt;br /&gt;&lt;br /&gt;&lt;span&gt;Yes.&lt;/span&gt;&lt;br /&gt;&lt;br /&gt;&lt;span&gt;&amp;gt; If so, you should be cleaning the D cache as well as invalidating it.&lt;/span&gt;&lt;br /&gt;&lt;br /&gt;&lt;code&gt;&lt;br /&gt;&lt;br /&gt;disablecache: mrc p15, 0, r15, c7, c14, 3 @ test, clean and invalidate&lt;br /&gt;&amp;#160;&amp;#160;&amp;#160;&amp;#160;&amp;#160;&amp;#160;&amp;#160;&amp;#160;&amp;#160;&amp;#160;&amp;#160;&amp;#160;&amp;#160;&amp;#160;&amp;#160; bne disablecache&lt;br /&gt;&lt;br /&gt;&amp;#160;&amp;#160;&amp;#160;&amp;#160;&amp;#160;&amp;#160;&amp;#160;&amp;#160;&amp;#160;&amp;#160;&amp;#160;&amp;#160;&amp;#160;&amp;#160;&amp;#160; mov r0,#0&amp;#160;&amp;#160;&amp;#160;&amp;#160;&amp;#160;&amp;#160;&amp;#160;&amp;#160;&amp;#160;&amp;#160;&amp;#160;&amp;#160;&amp;#160;&amp;#160;&amp;#160;&amp;#160; @ drain write buffer&lt;br /&gt;&amp;#160;&amp;#160;&amp;#160;&amp;#160;&amp;#160;&amp;#160;&amp;#160;&amp;#160;&amp;#160;&amp;#160;&amp;#160;&amp;#160;&amp;#160;&amp;#160;&amp;#160; mcr p15, 0, r0, c7, c10, 4&lt;br /&gt;&lt;br /&gt;@@@@&amp;#160;&amp;#160;&amp;#160;&amp;#160;&amp;#160;&amp;#160;&amp;#160;&amp;#160;&amp;#160;&amp;#160;&amp;#160; mcr p15, 0, r0, c7, c6, 0&amp;#160;&amp;#160;&amp;#160; @ invalidate dcache&lt;br /&gt;&lt;br /&gt;&amp;#160;&amp;#160;&amp;#160;&amp;#160;&amp;#160;&amp;#160;&amp;#160;&amp;#160;&amp;#160;&amp;#160;&amp;#160;&amp;#160;&amp;#160;&amp;#160;&amp;#160; mrc p15, 0, r0, c1, c0, 0&amp;#160;&amp;#160;&amp;#160; @ Disable Icache(12), Dcache(2) and MMU(0)&lt;br /&gt;&amp;#160;&amp;#160;&amp;#160;&amp;#160;&amp;#160;&amp;#160;&amp;#160;&amp;#160;&amp;#160;&amp;#160;&amp;#160;&amp;#160;&amp;#160;&amp;#160;&amp;#160; bic r0, r0, #4096&lt;br /&gt;&amp;#160;&amp;#160;&amp;#160;&amp;#160;&amp;#160;&amp;#160;&amp;#160;&amp;#160;&amp;#160;&amp;#160;&amp;#160;&amp;#160;&amp;#160;&amp;#160;&amp;#160; bic r0, r0, #5&lt;br /&gt;&amp;#160;&amp;#160;&amp;#160;&amp;#160;&amp;#160;&amp;#160;&amp;#160;&amp;#160;&amp;#160;&amp;#160;&amp;#160;&amp;#160;&amp;#160;&amp;#160;&amp;#160; mcr p15, 0, r0, c1, c0, 0&lt;br /&gt;&lt;br /&gt;&amp;#160;&amp;#160;&amp;#160;&amp;#160;&amp;#160;&amp;#160;&amp;#160;&amp;#160;&amp;#160;&amp;#160;&amp;#160;&amp;#160;&amp;#160;&amp;#160;&amp;#160; mov pc,lr&amp;#160;&amp;#160;&amp;#160;&amp;#160;&amp;#160;&amp;#160;&amp;#160;&amp;#160;&amp;#160;&amp;#160;&amp;#160;&amp;#160;&amp;#160;&amp;#160;&amp;#160;&amp;#160; @ return to SWI handler&lt;br /&gt;&lt;br /&gt;&lt;br /&gt;&lt;/code&gt;&lt;br /&gt;&lt;br /&gt;&lt;span&gt;Like this, in that order?&lt;/span&gt;&lt;br /&gt;&lt;br /&gt;&lt;br /&gt;&lt;br /&gt;&lt;br /&gt;&lt;span&gt;&amp;gt; Is the memory flat mapped?&lt;/span&gt;&lt;br /&gt;&lt;br /&gt;&lt;span&gt;Yes&lt;/span&gt;&lt;/div&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item></channel></rss>