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MMU problem on ARM926EJ-S
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MMU problem on ARM926EJ-S
Offline
Fabu Kosmi
over 7 years ago
Note: This was originally posted on 19th January 2011 at http://forums.arm.com
Hello community!
I've faced a problem while porting an OKL4 3.0 kernel to an ARM926EJ-S (Samsung S3C2412) board. I'm able to compile my kernel and load it into the boards RAM, but after starting it there is no reaction on my serial output. So I started to debug the source code. Due to the fact that I've got no JTAG and other debugging methods failed I'm using a LED based debugging method. I activate a LED by writing into its register. So I encountered a very early function in code in which the execution flow stucks:
It is a function that enables MMU, caching e.g.. I figured out: if I set the MMU disable bit in it I get out of this function. But if i enable the MMU, the flow stucks. The MMU is a necessary part of the kernel.
Before the MMU gets enabled the code has to perform several code specific operations:
###########################################################
start() must ensure that the platform is set to the following state:
- All caching is disabled.
- Virtual memory is disabled (MMU is turned off).
- Memory controllers are configured and running.
- The stack pointer is set.
- Other control registers required for further initialization are set.
###########################################################
After that the code enables MMU, caching e.g. considering following ARM926EJ-S specific requirements (ARM926EJ-S TM Revision: r0p5 Technical Reference Manual):
1. Program the TTB register (CP15 c2) and the domain access control register (CP15 c3).
2. Program first-level and second-level page tables as required, ensuring that a valid translation table is placed in memory at the location specified by the TTB register.
I could image the (a) problem refers to page table related issues.
Do you have an idea which problems I've to take into account?
Best regards,
Fabu
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jameer mulani
over 7 years ago
Note: This was originally posted on 21st January 2011 at
http://forums.arm.com
You need to invalidate TLB abd caches.
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jameer mulani
over 7 years ago
Note: This was originally posted on 21st January 2011 at
http://forums.arm.com
You need to invalidate TLB abd caches.
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