How JTAG take control of ARM core?

Note: This was originally posted on 29th July 2010 at http://forums.arm.com

Hello,

I have a question from customer regarding how to disable JTAG in their final product to prevent their application code from explosion from JTAG interface.

Since I am not familiar with JTAG debug module and ARM core interaction mechanism, I would like to know if there is any document talking about the JTAG debug detail procedure.

(1) We have a plan to disable the JTAG port during reset stage of the MCU, and enable it with the built-in ROM code in certain stage. I am not sure if it is workable, any attention needed?

(2) Is the system reset a must when entering JTAG debug mode? If not, please help explain the detail procedure on how JTAG take control of core.


Thanks a lot!
Parents
  • Note: This was originally posted on 4th August 2010 at http://forums.arm.com

    Hello,

    I have a question from customer regarding how to disable JTAG in their final product to prevent their application code from explosion from JTAG interface.

    Since I am not familiar with JTAG debug module and ARM core interaction mechanism, I would like to know if there is any document talking about the JTAG debug detail procedure.

    (1) We have a plan to disable the JTAG port during reset stage of the MCU, and enable it with the built-in ROM code in certain stage. I am not sure if it is workable, any attention needed?

    (2) Is the system reset a must when entering JTAG debug mode? If not, please help explain the detail procedure on how JTAG take control of core.


    Thanks a lot!


    Hi,
    If it is only ARM Chip then knowledge of Debug arch is more than enough..
    If you are talking from SoC point of view.. were you may hv zero, one or more other processor.. then you will need a special controller which uses Test Scan Cain to reach to all the programmable registers or processors debug ports in serial or parallel mannar.  This is typically called ICE. This ICE is connected to JTAG. JTAG is a way to connect this SoC to outside world to the ARM/ARM Based SoC.  In production devices typically this ICE is dissabled(using fuse) so that there will not be any 'insight' to outside world. :D

    Regards,
    Kedar Kulkarni
    [font="Verdana"][color="#FF8C00"]One day all digial world will be in my ARMs[/color].[/font]
Reply
  • Note: This was originally posted on 4th August 2010 at http://forums.arm.com

    Hello,

    I have a question from customer regarding how to disable JTAG in their final product to prevent their application code from explosion from JTAG interface.

    Since I am not familiar with JTAG debug module and ARM core interaction mechanism, I would like to know if there is any document talking about the JTAG debug detail procedure.

    (1) We have a plan to disable the JTAG port during reset stage of the MCU, and enable it with the built-in ROM code in certain stage. I am not sure if it is workable, any attention needed?

    (2) Is the system reset a must when entering JTAG debug mode? If not, please help explain the detail procedure on how JTAG take control of core.


    Thanks a lot!


    Hi,
    If it is only ARM Chip then knowledge of Debug arch is more than enough..
    If you are talking from SoC point of view.. were you may hv zero, one or more other processor.. then you will need a special controller which uses Test Scan Cain to reach to all the programmable registers or processors debug ports in serial or parallel mannar.  This is typically called ICE. This ICE is connected to JTAG. JTAG is a way to connect this SoC to outside world to the ARM/ARM Based SoC.  In production devices typically this ICE is dissabled(using fuse) so that there will not be any 'insight' to outside world. :D

    Regards,
    Kedar Kulkarni
    [font="Verdana"][color="#FF8C00"]One day all digial world will be in my ARMs[/color].[/font]
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