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Load/Store instruction cycle calculation
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Load/Store instruction cycle calculation
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Chintan Dave
over 7 years ago
Note: This was originally posted on 23rd February 2010 at http://forums.arm.com
Hi,
LDR instruction in cortex-m3 require 2 pipeline cycle means 6 clock cycle. 2-cycle is require for fetch and decode. In 3rd cycle address calculated and send to memory. Memory will sample the address in 4th clock cycle and put data on bus.In 5th clock cycle master will sample the input data and load register on negative edge of clock .Where the 6th clock cycle is utilise? (Here i am loading my register on negative edge of clock)
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