Performance Monitoring features for Cortex A8

Note: This was originally posted on 22nd January 2010 at http://forums.arm.com

Hi,

I am trying to use the performance counter feature in Cortex A8. I have downloaded the sample code given here : [url="http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.faqs/ka4237.html"]http://infocenter.arm.com/help/index.jsp?t...aqs/ka4237.html[/url]

I am able to find the cycles taken via the cycle counter. But when I set an event to count, the counter always printing zero. The register contents when viewed in RV Debugger shows the contents to be untouched(all excalamation marks!!)..even the cycle counter is not showing its contents.

It would be of great help if you could give some pointers regarding what to check for/what I might be missing out?

Thanks,
Smitha Joseph
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  • Note: This was originally posted on 5th December 2012 at http://forums.arm.com



    Has anyone been able to access performance event counters on Simulator?


    I am afraid the simulator is the cause of the problem.  The models provided by ARM only model the CCNT.  The registers for the configurable counters are present, but don;t do anything.


    I have been trying to use PMU with Cortex-A9 and the results are same i.e. unable to count the events occurred other than the cycle count.


    The surprising thing is that if I set event 0x11 (cycle count) with the above set of PMU registers, I am able to find the cycles taken through PMXEVCNTR (Event Count Register) which
    matches with the value of PMCCNTR (Cycle count register). All other events won't bring any value other than zero in counters. This confirms that the set of other co-processor registers such as PMCNTENSET, PMCNTENCLR, PMSELR, PMXEVTYPER, PMXENCNTR etc are also working from its model as I followed the following sequence to perform cycle counts.
    • Disable performance counters
    • Set what each event counter will count
    • Set cycle counter tick rate
    • Reset performance counters
    • Enable performance counters
    • Call function to profile
    • Disable performance counters
    • Read out performance counters
    • Check that performance counters did not overflow
Reply
  • Note: This was originally posted on 5th December 2012 at http://forums.arm.com



    Has anyone been able to access performance event counters on Simulator?


    I am afraid the simulator is the cause of the problem.  The models provided by ARM only model the CCNT.  The registers for the configurable counters are present, but don;t do anything.


    I have been trying to use PMU with Cortex-A9 and the results are same i.e. unable to count the events occurred other than the cycle count.


    The surprising thing is that if I set event 0x11 (cycle count) with the above set of PMU registers, I am able to find the cycles taken through PMXEVCNTR (Event Count Register) which
    matches with the value of PMCCNTR (Cycle count register). All other events won't bring any value other than zero in counters. This confirms that the set of other co-processor registers such as PMCNTENSET, PMCNTENCLR, PMSELR, PMXEVTYPER, PMXENCNTR etc are also working from its model as I followed the following sequence to perform cycle counts.
    • Disable performance counters
    • Set what each event counter will count
    • Set cycle counter tick rate
    • Reset performance counters
    • Enable performance counters
    • Call function to profile
    • Disable performance counters
    • Read out performance counters
    • Check that performance counters did not overflow
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