Arm Community
Site
Search
User
Site
Search
User
Groups
Arm Research
DesignStart
Education Hub
Graphics and Gaming
High Performance Computing
Innovation
Multimedia
Open Source Software and Platforms
Physical
Processors
Security
System
Software Tools
TrustZone for Armv8-M
中文社区
Blog
Announcements
Artificial Intelligence
Automotive
Healthcare
HPC
Infrastructure
Innovation
Internet of Things
Machine Learning
Mobile
Smart Homes
Wearables
Forums
All developer forums
IP Product forums
Tool & Software forums
Support
Open a support case
Documentation
Downloads
Training
Arm Approved program
Arm Design Reviews
Community Help
More
Cancel
Developer Community
Tools and Software
Software Tools
Jump...
Cancel
Software Tools
Arm Development Studio forum
Testing Data Cache of ARM926EJ-S
Tools, Software and IDEs blog
Forums
Videos & Files
Help
Jump...
Cancel
New
Replies
2 replies
Subscribers
126 subscribers
Views
1395 views
Users
0 members are here
Related
Testing Data Cache of ARM926EJ-S
Offline
mel mel
over 7 years ago
Note: This was originally posted on 26th November 2009 at http://forums.arm.com
Hi,
I have an issue testing data cache for ARM926EJ-S used by AT91SAM9XE and AT91SAM9G20.
As you know, AT91SAM9XE has the flash memory and in this case I'm trying to test data cache of the architecture, in these conditions:
1. MMU and Page Table enabled
2. Round Robin replacement enabled
3. The code of the main program is loaded in the flash memory
4. The data pattern for the test are read and written in SDRAM
Under these conditions the result of the test for data cache is good.
When I use the AT91SAM9G20, that no have flash memory on board, I'm constrained to load the code of the main program in another memory.
In the first case I choose to load the main program, in the SDRAM, and I try to test data cache of the architecture, in these conditions:
1. MMU and Page Table enabled
2. Round Robin replacement enabled
3. The code of the main program is loaded in SDRAM
4. The data pattern for the test are read and written in SDRAM
The result in this case is a cache fault.
In the second mode of AT91SAM9G20, I choose to load the code of main program in one of the two SRAM region, while the data pattern are read and written always in SDRAM.
Well, in this case, the same test works properly.
I want to know if someone have this problem and why if I load in the same memory (SDRAM) instructions and data, the test fails.
Is there a particular reason?
Thanks in advance for your help
More questions in this forum
By title
By date
By reply count
By view count
By most asked
By votes
By quality
Descending
Ascending
All recent questions
Unread questions
Questions you've participated in
Questions you've asked
Unanswered questions
Answered questions
Questions with suggested answers
Questions with no replies
Suggested Answer
How to view SFRs in DS during debugging?
0
1941
views
1
reply
Latest
1 month ago
by
Ronan Synnott
Answered
Dual-core debugging in DS
0
4845
views
2
replies
Latest
1 month ago
by
Ivan Savvateev
Answered
Failure to get an evaluation license with error Unable to execute API call /api/v1/connect
0
5767
views
3
replies
Latest
1 month ago
by
Tim Holt
Suggested Answer
DS52020.0 connection to Musca-A/B boards not working
0
Arm Development Studio
Musca-A
6786
views
4
replies
Latest
1 month ago
by
Daniel Oliveira
Suggested Answer
Positioning a function in a Position Independent Executable for ARMV8
0
7357
views
3
replies
Latest
2 months ago
by
Stephen Theobald
<
>
View all questions in Arm Development Studio forum