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<?xml-stylesheet type="text/xsl" href="https://community.arm.com/utility/feedstylesheets/rss.xsl" media="screen"?><rss version="2.0" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:slash="http://purl.org/rss/1.0/modules/slash/" xmlns:wfw="http://wellformedweb.org/CommentAPI/"><channel><title>Cortex M3 - how to enter Privileged Mode?</title><link>https://community.arm.com/developer/tools-software/tools/f/armds-forum/634/cortex-m3---how-to-enter-privileged-mode</link><description> Note: This was originally posted on 15th July 2009 at http://forums.arm.com Hi, I try to get an implementation that disables all interrupts up to an specific level. I use the BASEPRI for this. However the disabling doesnt work, all interrupts are passing</description><dc:language>en-US</dc:language><generator>Telligent Community 10</generator><item><title>RE: Cortex M3 - how to enter Privileged Mode?</title><link>https://community.arm.com/thread/1594?ContentTypeID=1</link><pubDate>Wed, 11 Sep 2013 10:59:01 GMT</pubDate><guid isPermaLink="false">dd9e70c8-6d3c-4c71-b136-2456382a7b5c:8e3457c0-a7aa-4e46-ad76-5afe04f3ca7b</guid><dc:creator>guestposter guestposter</dc:creator><description>&lt;div&gt;&lt;i&gt;Note: This was originally posted on 16th July 2009 at &lt;a href="http://forums.arm.com"&gt;http://forums.arm.com&lt;/a&gt;&lt;/i&gt;&lt;br /&gt;&lt;br /&gt;&lt;span&gt;Thanks. I checked our support system and found that it is&lt;/span&gt;&lt;br /&gt;&lt;span&gt; a known documentation errata on the r1p1 TRM.&lt;/span&gt;&lt;br /&gt;&lt;br /&gt;&lt;span&gt;regards,&lt;/span&gt;&lt;br /&gt;&lt;span&gt;Joseph&lt;/span&gt;&lt;/div&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: Cortex M3 - how to enter Privileged Mode?</title><link>https://community.arm.com/thread/1593?ContentTypeID=1</link><pubDate>Wed, 11 Sep 2013 10:59:01 GMT</pubDate><guid isPermaLink="false">dd9e70c8-6d3c-4c71-b136-2456382a7b5c:ff270373-fdc0-481b-8e34-2e3f3eca3b70</guid><dc:creator>guestposter guestposter</dc:creator><description>&lt;div&gt;&lt;i&gt;Note: This was originally posted on 15th July 2009 at &lt;a href="http://forums.arm.com"&gt;http://forums.arm.com&lt;/a&gt;&lt;/i&gt;&lt;br /&gt;&lt;br /&gt;&lt;span&gt;Hi Ssss,&lt;/span&gt;&lt;br /&gt;&lt;br /&gt;&lt;span&gt;CONTROL[0] = 0 is privileged mode&lt;/span&gt;&lt;br /&gt;&lt;span&gt;CONTROL[0] = 1 is user mode&lt;/span&gt;&lt;br /&gt;&lt;br /&gt;&lt;span&gt;Could you tell me which page in TRM you are referring to?&lt;/span&gt;&lt;br /&gt;&lt;span&gt;(and which revision of the TRM).&lt;/span&gt;&lt;br /&gt;&lt;br /&gt;&lt;span&gt;From page 2-3 of Cortex-M3 revision 2 TRM:&lt;/span&gt;&lt;br /&gt;&lt;span&gt;&amp;quot;Thread mode is privileged out of reset, but you can change it to user or unprivileged by&lt;/span&gt;&lt;br /&gt;&lt;span&gt;setting the CONTROL[0] bit using the MSR instruction.&amp;quot;&lt;/span&gt;&lt;br /&gt;&lt;br /&gt;&lt;span&gt;That&amp;#39;s why the CONTROL register is 0x00 out of reset (privileged).&lt;/span&gt;&lt;br /&gt;&lt;span&gt;Setting CONTROL[0] to 1 will change it to user mode.&lt;/span&gt;&lt;br /&gt;&lt;br /&gt;&lt;span&gt;To use BASEPRI, you need to set it to a non-zero value.&amp;#160; For example,&lt;/span&gt;&lt;br /&gt;&lt;span&gt;if 16 priority levels are available, it will be 0x10, 0x20, ... 0xF0.&lt;/span&gt;&lt;br /&gt;&lt;span&gt;If you set it to 0x00, the BASEPRI masking function is disabled.&lt;/span&gt;&lt;br /&gt;&lt;br /&gt;&lt;span&gt;However, by default all interrupts are at priority level 0. So they are higher&lt;/span&gt;&lt;br /&gt;&lt;span&gt;priority than any BASEPRI value. As a result, no matter what value you&lt;/span&gt;&lt;br /&gt;&lt;span&gt;set BASEPRI to, the interrupts will still get through.&amp;#160; Therefore, BASEPRI&lt;/span&gt;&lt;br /&gt;&lt;span&gt;can only mask a interrupt if the priority level of the interrupt is not set to 0.&lt;/span&gt;&lt;br /&gt;&lt;br /&gt;&lt;span&gt;To mask interrupts with priority level 0, you need to use PRIMASK.&lt;/span&gt;&lt;br /&gt;&lt;span&gt;The easiest way to set PRIMASK is using (in assembly)&lt;/span&gt;&lt;br /&gt;&lt;span&gt;&amp;#160;&amp;#160; CPSID&amp;#160; i&lt;/span&gt;&lt;br /&gt;&lt;span&gt;or in C:&lt;/span&gt;&lt;br /&gt;&lt;span&gt;&amp;#160; __disable_irq();&lt;/span&gt;&lt;br /&gt;&lt;br /&gt;&lt;span&gt;regards,&lt;/span&gt;&lt;br /&gt;&lt;span&gt;Joseph&lt;/span&gt;&lt;/div&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: Cortex M3 - how to enter Privileged Mode?</title><link>https://community.arm.com/thread/1592?ContentTypeID=1</link><pubDate>Wed, 11 Sep 2013 10:59:01 GMT</pubDate><guid isPermaLink="false">dd9e70c8-6d3c-4c71-b136-2456382a7b5c:1b153946-3861-450d-a883-1df18372bfd4</guid><dc:creator>Sebastian Gaertner</dc:creator><description>&lt;div&gt;&lt;i&gt;Note: This was originally posted on 16th July 2009 at &lt;a href="http://forums.arm.com"&gt;http://forums.arm.com&lt;/a&gt;&lt;/i&gt;&lt;br /&gt;&lt;br /&gt;&lt;span&gt;Hi Joseph&lt;/span&gt;&lt;br /&gt;&lt;br /&gt;&lt;span&gt;thanks for the hints with the priorities, I understand better now. Seems my priority&amp;#160; is still set to 0 - so I see still the interrupt.&lt;/span&gt;&lt;br /&gt;&lt;br /&gt;&lt;span&gt;Yes, here we have two different versions of the CONTROl[0] description. This is a part of the TRM I used:&lt;/span&gt;&lt;br /&gt;&lt;br /&gt;&lt;span&gt;Cortex&amp;#8482;-M3 TRM Revision: r1p1:&lt;/span&gt;&lt;br /&gt;&lt;br /&gt;&lt;span&gt;Thread mode is privileged out of reset, but you can change it to user or unprivileged by&lt;/span&gt;&lt;br /&gt;&lt;strong&gt;clearing &lt;/strong&gt;&lt;span&gt;the CONTROL[0] bit using the MSR instruction.&lt;/span&gt;&lt;/div&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item></channel></rss>