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Can cortex-A9 issue two load/store per cycle?
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Can cortex-A9 issue two load/store per cycle?
Offline
Peng Yuan
over 7 years ago
Note: This was originally posted on 25th August 2012 at http://forums.arm.com
Hi All,
Can cortex-A9 issue two load/store per cycle?
If yes, the following sequence shoud be scheduled to interleave str and data processing insns. right?
add r5, r0, r1
mov r3, r0
str r3, [sp]
str r3, [sp, #4]
str r3, [sp, #8]
==>
str r3, [sp]
add r5, r0, r1
str r3, [sp, #4]
mov r3, r0
str r3, [sp, #8]
I find commnet "Only one load/store instruction can be issued per cycle" in cortex-a8 description in GCC. But I'm not sure if it is ture in cortex-a9.
Thanks a ton!!
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Offline
Gilead Kutnick
over 7 years ago
Note: This was originally posted on 27th August 2012 at
http://forums.arm.com
It can't perform two memory operations in the same cycle (neither two loads, two stores, nor one load plus one store), but you won't necessarily see a difference in manually reordering the instruction stream because Cortex-A9 has at least some ability to execute out of order.
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Gilead Kutnick
over 7 years ago
Note: This was originally posted on 27th August 2012 at
http://forums.arm.com
It can't perform two memory operations in the same cycle (neither two loads, two stores, nor one load plus one store), but you won't necessarily see a difference in manually reordering the instruction stream because Cortex-A9 has at least some ability to execute out of order.
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