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Setting up uvision4 debugger with Cortex-M1 on Altera Cyclone III
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Setting up uvision4 debugger with Cortex-M1 on Altera Cyclone III
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Siew Kei Lam
over 7 years ago
Note: This was originally posted on 21st June 2011 at http://forums.arm.com
I am trying to setup the uvision4 debugger to communicate with Cortex M1 on Altera Cyclone III through the USB JTAG interface. I have observed from the Cortex-M1 development kit that this can be done by instantiating the Virtual JTAG megafunction and implementing a glue logic to interface the Virtual JTAG with the Cortex-M1 RTL. Unfortunately, the Verilog description of the glue logic is not visible.
Can anyone give me some pointers on how to go about designing the glue logic between Virtual JTAG and Cortex-M1? Or is there another alternative to this? Thanks.
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Joseph Yiu
over 7 years ago
Note: This was originally posted on 22nd June 2011 at
http://forums.arm.com
Hi there,
Are you using Cortex-M1 Verilog RTL source, or Cortex-M1 Altera development kit?
Joseph
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Siew Kei Lam
over 7 years ago
Note: This was originally posted on 23rd June 2011 at
http://forums.arm.com
Hi Joseph,
I am using Cortex-M1 Verilog RTL source code. I have generated the bitstream using Altera tools and downloaded it onto the Altera FPGA. However, uvision4 is unable to detect the core on the FPGA. I am pretty sure that I have generated the bitstream correctly.
When I analyzed the files provided by Cortex-M1 Altera development kit, I realized that they have instantiated the Virtual JTAG megafunction and implemented a glue logic to interface the Virtual JTAG with the Cortex-M1. This glue logic is encrypted so I have no idea how it works.
Thanks and regards,
Siew Kei
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Joseph Yiu
over 7 years ago
Note: This was originally posted on 23rd June 2011 at
http://forums.arm.com
I have discussed with the engineer who worked on this. When Cortex-M1 was developed, the Virtual JTAG detail specification was not open to public. As a result, we were unable to include the glue logic to the Cortex-M1 RTL package.
You should be able to bring out the JTAG/Serial Wire signals to the FPGA top level (you need to add a tristate buffer to SWIO), then you should be able to connect it to the debugger using Keil ULINK, Segger J-Link or other debuggers, using this separated JTAG interface.
Alternatively you can contact our support team to see if we can provide the detail of this glue logic to you.
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Siew Kei Lam
over 7 years ago
Note: This was originally posted on 24th June 2011 at
http://forums.arm.com
Hi Joseph,
Actually, we are trying to get uVision4 to communicate with Cortex-M1 on the FPGA through the USB ByteBlaster. This is possible for the Cortex-M1 Altera development kit.
I will contact the support team to see if they can provide the glue logic. Thanks the suggestions.
Regards,
Siew Kei
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