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<?xml-stylesheet type="text/xsl" href="https://community.arm.com/utility/feedstylesheets/rss.xsl" media="screen"?><rss version="2.0" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:slash="http://purl.org/rss/1.0/modules/slash/" xmlns:wfw="http://wellformedweb.org/CommentAPI/"><channel><title>DS-5 connect fail when cortex-r5 is in lock-step mode</title><link>https://community.arm.com/developer/tools-software/tools/f/armds-forum/47607/ds-5-connect-fail-when-cortex-r5-is-in-lock-step-mode</link><description> Dear All, 
 I am using DS-5 to debug Zynq UltraScale+ MPSoC. 
 Evevrything goes well, but when the Cortex-r5 is run in lock-step mode, DS-5 cannot be connected(Cannot connect to A53 or R5). 
 When the r5 is in splt mode or r5 is powerd off, DS-5 work</description><dc:language>en-US</dc:language><generator>Telligent Community 10</generator><item><title>RE: DS-5 connect fail when cortex-r5 is in lock-step mode</title><link>https://community.arm.com/thread/167846?ContentTypeID=1</link><pubDate>Thu, 01 Oct 2020 08:17:44 GMT</pubDate><guid isPermaLink="false">dd9e70c8-6d3c-4c71-b136-2456382a7b5c:cc941bf4-5332-4ef3-942d-4d1c4d951e7e</guid><dc:creator>Stuart Hirons</dc:creator><description>&lt;p&gt;This is in fact by design and the Xilinx answer record on this issue is at&lt;/p&gt;
&lt;p&gt;&lt;/p&gt;
&lt;p&gt;&lt;a href="https://www.xilinx.com/support/answers/69183.html"&gt;https://www.xilinx.com/support/answers/69183.html&lt;/a&gt;&lt;/p&gt;
&lt;p&gt;&lt;/p&gt;
&lt;p&gt;This affects any debugger, not just Arm DS!&lt;/p&gt;
&lt;p&gt;Regards,&lt;/p&gt;
&lt;p&gt;Stuart&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: DS-5 connect fail when cortex-r5 is in lock-step mode</title><link>https://community.arm.com/thread/167595?ContentTypeID=1</link><pubDate>Mon, 21 Sep 2020 07:26:10 GMT</pubDate><guid isPermaLink="false">dd9e70c8-6d3c-4c71-b136-2456382a7b5c:8cd36b58-2d32-48ca-bdc0-f6dbab9e0b37</guid><dc:creator>Stuart Hirons</dc:creator><description>&lt;p&gt;HI,&lt;/p&gt;
&lt;p&gt;I am having difficulty setting the environment up for this, so can you please raise your issue at&lt;/p&gt;
&lt;p&gt;&lt;/p&gt;
&lt;p&gt;&lt;a href="https://developer.arm.com/support"&gt;https://developer.arm.com/support&lt;/a&gt;&lt;/p&gt;
&lt;p&gt;&lt;/p&gt;
&lt;p&gt;and make it clear that is related to this post and I&amp;#39;ll pick it up ASAP.&lt;/p&gt;
&lt;p&gt;&lt;/p&gt;
&lt;p&gt;Sorry about this.&lt;/p&gt;
&lt;p&gt;Regards,&lt;/p&gt;
&lt;p&gt;Stuart&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: DS-5 connect fail when cortex-r5 is in lock-step mode</title><link>https://community.arm.com/thread/167519?ContentTypeID=1</link><pubDate>Thu, 17 Sep 2020 06:58:50 GMT</pubDate><guid isPermaLink="false">dd9e70c8-6d3c-4c71-b136-2456382a7b5c:315c636f-7755-4924-8de4-3140f8d9eaa2</guid><dc:creator>Jeffrey_lin</dc:creator><description>&lt;p&gt;Thanks for your effort. Please let me know if any update.&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: DS-5 connect fail when cortex-r5 is in lock-step mode</title><link>https://community.arm.com/thread/167511?ContentTypeID=1</link><pubDate>Wed, 16 Sep 2020 15:59:31 GMT</pubDate><guid isPermaLink="false">dd9e70c8-6d3c-4c71-b136-2456382a7b5c:11375154-b4be-4e9c-85bd-d4947cd50964</guid><dc:creator>Stuart Hirons</dc:creator><description>&lt;p&gt;Hi, still battling with tools I am afraid, I need to install Vitis in order to generate a boot image for the Cortex-R5.&lt;/p&gt;
&lt;p&gt;Sorry about this.&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: DS-5 connect fail when cortex-r5 is in lock-step mode</title><link>https://community.arm.com/thread/167488?ContentTypeID=1</link><pubDate>Tue, 15 Sep 2020 16:29:50 GMT</pubDate><guid isPermaLink="false">dd9e70c8-6d3c-4c71-b136-2456382a7b5c:eded7044-52dc-4a43-8a75-b12c3b6af5d3</guid><dc:creator>Stuart Hirons</dc:creator><description>&lt;p&gt;Hi sorry, I am still sorting out a few tools issues to generate the appropriate SDCard image to boot the R5_0. &lt;/p&gt;
&lt;p&gt;I&amp;#39;ll let you know once I have any update&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: DS-5 connect fail when cortex-r5 is in lock-step mode</title><link>https://community.arm.com/thread/167481?ContentTypeID=1</link><pubDate>Tue, 15 Sep 2020 06:21:27 GMT</pubDate><guid isPermaLink="false">dd9e70c8-6d3c-4c71-b136-2456382a7b5c:cacc5fbb-3201-4893-9a6a-9417d5dd11a8</guid><dc:creator>Jeffrey_lin</dc:creator><description>&lt;p&gt;Hi&amp;nbsp;Stuart Hirons&lt;/p&gt;
&lt;p&gt;&lt;span class="user-name"&gt;Sorry for disturbing you. Is there any update for me?&lt;/span&gt;&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: DS-5 connect fail when cortex-r5 is in lock-step mode</title><link>https://community.arm.com/thread/167435?ContentTypeID=1</link><pubDate>Fri, 11 Sep 2020 02:42:47 GMT</pubDate><guid isPermaLink="false">dd9e70c8-6d3c-4c71-b136-2456382a7b5c:b2b6751a-277b-4dd5-9220-f2e777a7e3d4</guid><dc:creator>Jeffrey_lin</dc:creator><description>&lt;p&gt;Hi,&lt;/p&gt;
&lt;p&gt;Thanks for your support.&lt;/p&gt;
&lt;p&gt;My development board is our own creation, and is based on Xilinx&amp;nbsp;XCZU6CG-FFVB1156E SoC (&lt;a href="https://www.digikey.com/product-detail/en/xilinx-inc/XCZU6CG-2FFVB1156E/XCZU6CG-2FFVB1156E-ND/6817801"&gt;https://www.digikey.com/product-detail/en/xilinx-inc/XCZU6CG-2FFVB1156E/XCZU6CG-2FFVB1156E-ND/6817801&lt;/a&gt;).&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: DS-5 connect fail when cortex-r5 is in lock-step mode</title><link>https://community.arm.com/thread/167425?ContentTypeID=1</link><pubDate>Thu, 10 Sep 2020 14:33:43 GMT</pubDate><guid isPermaLink="false">dd9e70c8-6d3c-4c71-b136-2456382a7b5c:48789d4a-c781-44dc-848c-b63842f09d40</guid><dc:creator>Stuart Hirons</dc:creator><description>&lt;p&gt;Hi again ,&lt;/p&gt;
&lt;p&gt;Thanks for the update and the confirmation of RPU_GLBL_CNTL value.&lt;/p&gt;
&lt;p&gt;Using a Xilinx ZCU102 dev board and booting from SDCard with the A53_0 performing the boot, I am able to set up the R5&amp;#39;s to be in lockstep mode with a DS-5 pre-connect script.&lt;/p&gt;
&lt;p&gt;I can subsequently connect with DS-5 v5.29.2 and a DSTREAM unit (running 4.34.0 build 13 firmware as included with DS-5).&lt;/p&gt;
&lt;p&gt;Please see the screenshot below :&lt;/p&gt;
&lt;p&gt;&lt;img alt="R5_0 connected on ZCU102 in lockstep" src="/resized-image/__size/640x480/__key/communityserver-discussions-components-files/15/Ultrascale-R5_5F00_0-connect-lockstep.jpg" /&gt;&lt;/p&gt;
&lt;p&gt;Because the R5&amp;#39;s are powered down prior to my connection, I used a script to set the R5&amp;#39;s up to be in lockstep mode. As hopefully can be seen above, I can connect to R5_0 OK, and then if I also try connecting to R5_1 then as expected, it is not available and is being indicated as powered-down by DS-5.&lt;/p&gt;
&lt;p&gt;&lt;/p&gt;
&lt;p&gt;So something is different about the way our targets are being initialised here I feel.&lt;/p&gt;
&lt;p&gt;To investigate this further I will have to create an sdcard with the Cortex-R5 being the boot processor, but this might take me some little time as I do not have the required tools setup at the moment, it would be sometime next week before I could make much progress I&amp;#39;m afraid.&lt;/p&gt;
&lt;p&gt;In the meantime, perhaps there is something different about the CPUs have been initialised with my script and the Xilinx tools ??&lt;/p&gt;
&lt;p&gt;&lt;/p&gt;
&lt;p&gt;Also, could you just clarify which development board you are using please (weblink, part number...) ?&lt;/p&gt;
&lt;p&gt;Regards,&lt;/p&gt;
&lt;p&gt;Stuart&lt;/p&gt;
&lt;p&gt;&lt;/p&gt;
&lt;p&gt;&lt;/p&gt;
&lt;p&gt;&lt;/p&gt;
&lt;p&gt;&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: DS-5 connect fail when cortex-r5 is in lock-step mode</title><link>https://community.arm.com/thread/167422?ContentTypeID=1</link><pubDate>Thu, 10 Sep 2020 11:31:42 GMT</pubDate><guid isPermaLink="false">dd9e70c8-6d3c-4c71-b136-2456382a7b5c:5c20c095-b975-4be0-b04e-1bc72b3f39f4</guid><dc:creator>Jeffrey_lin</dc:creator><description>&lt;p&gt;Hi,&lt;/p&gt;
&lt;p&gt;Thanks for your reply.Please see my reply below.&lt;/p&gt;
&lt;p&gt;- what version of DS-5/Arm DS is in use&lt;/p&gt;
&lt;p&gt;&amp;gt;&amp;gt;&amp;gt;&lt;/p&gt;
&lt;p&gt;DS-5 Ultimate Edition&lt;br /&gt;Version: 5.29.2&lt;br /&gt;Build number: 5292005&lt;/p&gt;
&lt;p&gt;- are you using the ZCU102 or Ultra96 board or &amp;#39;something else&amp;#39; ?&lt;/p&gt;
&lt;p&gt;&amp;gt;&amp;gt;&amp;gt;I am using CG serial.&lt;/p&gt;
&lt;p&gt;- how are you booting the target board : from SDCard, flash, JTAG... ?&lt;/p&gt;
&lt;p&gt;&amp;gt;&amp;gt;&amp;gt;boot from emmc.&lt;/p&gt;
&lt;p&gt;- how are you configuring the R5&amp;#39;s to be in lockstep mode, specifically what is the RPU_GLBL_CNTL set to, and when during the boot process ?&lt;/p&gt;
&lt;p&gt;&amp;gt;&amp;gt;&amp;gt;set the destination cpu is &amp;quot;r5-lockstep&amp;quot; when generated boot.bin. The value of&amp;nbsp;&lt;span&gt;&amp;nbsp;RPU_GLBL_CNTL&amp;nbsp; is 0x50.&lt;/span&gt;&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: DS-5 connect fail when cortex-r5 is in lock-step mode</title><link>https://community.arm.com/thread/167421?ContentTypeID=1</link><pubDate>Thu, 10 Sep 2020 11:12:15 GMT</pubDate><guid isPermaLink="false">dd9e70c8-6d3c-4c71-b136-2456382a7b5c:7110e7f9-5f50-4bf1-920f-80c2db3e7522</guid><dc:creator>Stuart Hirons</dc:creator><description>&lt;p&gt;Hi,&lt;/p&gt;
&lt;p&gt;Sorry to hear about this.&lt;/p&gt;
&lt;p&gt;&lt;/p&gt;
&lt;p&gt;Can you please confirm a couple of things here :&lt;/p&gt;
&lt;p&gt;- what version of DS-5/Arm DS is in use&lt;/p&gt;
&lt;p&gt;- are you using the ZCU102 or Ultra96 board or &amp;#39;something else&amp;#39; ?&lt;/p&gt;
&lt;p&gt;- how are you booting the target board : from SDCard, flash, JTAG... ?&lt;/p&gt;
&lt;p&gt;- how are you configuring the R5&amp;#39;s to be in lockstep mode, specifically what is the RPU_GLBL_CNTL set to, and when during the boot process ?&lt;/p&gt;
&lt;p&gt;&lt;/p&gt;
&lt;p&gt;If you don&amp;#39;t want to discuss this publicly then please a support ticket at &lt;a href="https://developer.arm.com/support"&gt;https://developer.arm.com/support&lt;/a&gt;&lt;/p&gt;
&lt;p&gt;&lt;/p&gt;
&lt;p&gt;regards,&lt;/p&gt;
&lt;p&gt;Stuart&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item></channel></rss>