I got a couple of very basic questions about the example library came with DS-5:
Background - Arria 10 SoC FPGA is used on my board.
1. Does the example project "startup_Cortex_A9_AC5-FVP" run from Arria 10 SoC FPGA intel RAM or from external RAM? For example, DDR4 DRAM.
2. I think the "Examples & Programming Libraries -> Examples -> Bare-Metal Boards- > Altera-Arria-10_RAM" run from external memory, e.g. DDR4, right?
3. If it's assuming UDIMM, do I need changing anything in the code as there is DDR4 components on my board?
Also, more Intel SoC FPGA examples and DS scripts can be found here: https://rocketboards.org/
Really appreciate the help as first time user.
I do see the code at 0x80000000 ~ 0x80002054 by default and the code was relocated accordingly after build with changing the scatter file to start from 0x00000000.
I seems able to modify the contents from Memory View from 0x80000000 and above.
I like to confirm was the actual external memory got modified or not. Thank you.
If you modify the scatter file, then the code will have to be recompiled and re-linked before the axf/elf file will be modified to reflect the change in the memory map. Changing the scatter file alone will not change the compiled code.
If you double-click on the .axf/.elf file in the project window, this will open an elf viewer and you can see the layout of the resultant output of the linker.
Let try again.
It seems not connecting to the real hardware by running this example.
Could this example project runs on the real hardware?
For now, I like to test and verify the DDR4 memory on the board hopefully with Memory Viewer. Thank you.
That is correct the "startup_Cortex_A9_AC5-FVP" example is configured to run in the Fixed Virtual Platform and not on the Arria 10 SoC. The "Altera-Arria-10_RAM" example is configured to run on the real hardware.
You can create a new debug configuration for the startup_Cortex_A9_AC5-FVP example and make it run on the Arria 10 SoC, but the other example is already setup to do this.
Also, please note that neither of these examples sets up the DDR4 - the DDR controller is NOT configured by these examples. The DDR4 will have to be configured separately by the FPGA bitstream or you will have to modify the examples with code to setup the DDR controller.
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