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TrustZone with PL310
Offline
syuji biwa
over 7 years ago
Note: This was originally posted on 17th August 2013 at http://forums.arm.com
I plan to use a simple 'TrustZone Monitor' with PL310(L2CC).
In non-secure, I will play a Linux-Kernel.
One problem.
1. PL310's background-operation(inv.way etc..) is executing in non-secure.
2. By secure-interrupt, dispatch to secure.
3. In secure, try to execute a write-operation to PL310' register.
May be happen 'DATA-ABORT'.
Do I must control exclusive PL310 secure and non-secure ?
Please help me.
Parents
Offline
syuji biwa
over 7 years ago
Note: This was originally posted on 21st August 2013 at
http://forums.arm.com
So, Always(is not related secure and non-secure), need the exclusive control?
I understand.
I tested follow.
1. execute PL310's background operation.
2. As soon as, execute cache_sync operation.(write to PL310 register)
3. DATA-ABORT occured.
one more,
1. (CORE0) execute PL310's background operation.
2. (CORE0) wait for complete background operation.(read from PL310 register) (never DATA-ABORT)
3. (CORE1) execute cache_sync operation.(write to PL310 register)
4. (CORE1) DATA-ABORT occured.
my problem is How implement a SecureOS.
In generary, non-secureOS is allows FIQ-interrupt always.(can not disable FIQ.)
Linux's spin_lock_irqsave() can not disable FIQ.
So that, Between secure and non-secure, Can exclusive-control implement?
------------------------------------------------------------------------
Sorry, 「non-cache and device access order」question is written independently.
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Offline
syuji biwa
over 7 years ago
Note: This was originally posted on 21st August 2013 at
http://forums.arm.com
So, Always(is not related secure and non-secure), need the exclusive control?
I understand.
I tested follow.
1. execute PL310's background operation.
2. As soon as, execute cache_sync operation.(write to PL310 register)
3. DATA-ABORT occured.
one more,
1. (CORE0) execute PL310's background operation.
2. (CORE0) wait for complete background operation.(read from PL310 register) (never DATA-ABORT)
3. (CORE1) execute cache_sync operation.(write to PL310 register)
4. (CORE1) DATA-ABORT occured.
my problem is How implement a SecureOS.
In generary, non-secureOS is allows FIQ-interrupt always.(can not disable FIQ.)
Linux's spin_lock_irqsave() can not disable FIQ.
So that, Between secure and non-secure, Can exclusive-control implement?
------------------------------------------------------------------------
Sorry, 「non-cache and device access order」question is written independently.
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