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Questions about code benchmark difference between A8 and A15
Offline
Adam Yao
over 7 years ago
Note: This was originally posted on 1st May 2013 at http://forums.arm.com
[size="3"]Hi all,
I tested some protocol stack code's benchmark in Cortex A8 and A15. The code is same and I enabled L1/L2 cache and branch prediction in both CPUs (I placed all the codes and data in DDR and configurated DDR's MMU attribute to WB&WA for both L1 and L2 cache). Basicly A15's result is bettern than A8, but there is something I can not explain. The resut is as below:
A8 A15
Overall cycles 71821 30057
L1I cache miss 469 431
L1D cache miss 1015 139
L2 cache read miss 78 584
L2 cache write miss 247 26
mis-predicted/no predicted branch 469 217
predicted branch 1015 11385
What confused me are:
[/size](1) Why A15's L1D cache miss number is much lower than A8, both CPU's L1D cache is 32K? So what cause A15's L1D performance improvement?
(2) Why A15's L2 cache read miss number is much higher than A8?
(3) For branch prediction, why the sum of predicted and not predicted branch number is not equal in A8 and A15 and why A15's number is about 10 times A8's number?
Wait for a reasonable explanation.
Thank you.
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