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<?xml-stylesheet type="text/xsl" href="https://community.arm.com/utility/feedstylesheets/rss.xsl" media="screen"?><rss version="2.0" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:slash="http://purl.org/rss/1.0/modules/slash/" xmlns:wfw="http://wellformedweb.org/CommentAPI/"><channel><title>ARM cortex a7 cache maintenance operation</title><link>https://community.arm.com/developer/tools-software/tools/f/armds-forum/1123/arm-cortex-a7-cache-maintenance-operation</link><description> Note: This was originally posted on 11th March 2013 at http://forums.arm.com Hi all: I move on my last project of ARM cortex-a9 to now cortex-a7, here is a small questions. In A9, seems the pl310 have the ability to invalidate the entire L2 cache by</description><dc:language>en-US</dc:language><generator>Telligent Community 10</generator><item><title>RE: ARM cortex a7 cache maintenance operation</title><link>https://community.arm.com/thread/3501?ContentTypeID=1</link><pubDate>Wed, 11 Sep 2013 11:08:56 GMT</pubDate><guid isPermaLink="false">dd9e70c8-6d3c-4c71-b136-2456382a7b5c:a6e5b5e7-cca2-4fe5-810f-1b3a6df4f6e7</guid><dc:creator>Peter Harris</dc:creator><description>&lt;div&gt;&lt;i&gt;Note: This was originally posted on 11th March 2013 at &lt;a href="http://forums.arm.com"&gt;http://forums.arm.com&lt;/a&gt;&lt;/i&gt;&lt;br /&gt;&lt;br /&gt;&lt;span&gt;Also worth noting that once the CPU is running in multi-core SMP mode you cannot use set-way operations for D-side cache maintenance. You must use clean by MVA to ensure that all of the cache coherency snoops get picked up correctly.&lt;/span&gt;&lt;/div&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: ARM cortex a7 cache maintenance operation</title><link>https://community.arm.com/thread/3500?ContentTypeID=1</link><pubDate>Wed, 11 Sep 2013 11:08:56 GMT</pubDate><guid isPermaLink="false">dd9e70c8-6d3c-4c71-b136-2456382a7b5c:dde8b76a-2b6d-488d-b7b7-bc66b5ce92f4</guid><dc:creator>Martin Weidmann</dc:creator><description>&lt;div&gt;&lt;i&gt;Note: This was originally posted on 11th March 2013 at &lt;a href="http://forums.arm.com"&gt;http://forums.arm.com&lt;/a&gt;&lt;/i&gt;&lt;br /&gt;&lt;br /&gt;&lt;span&gt;AFAIK there is no alternative.&amp;#160; If you want to invalidate the entire L2 on an A7/A15 you have to use set/way operations.&lt;/span&gt;&lt;br /&gt;&lt;br /&gt;&lt;span&gt;That said, unless you &lt;/span&gt;&lt;strong&gt;L2RSTDISABLE &lt;/strong&gt;&lt;span&gt;high the L2 will be automatically invalidated at reset.&amp;#160; So there is no need for standard/basic init code to invalidate the L2,&lt;/span&gt;&lt;br /&gt;&lt;br /&gt;&lt;br /&gt;&lt;/div&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item></channel></rss>