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<?xml-stylesheet type="text/xsl" href="https://community.arm.com/utility/feedstylesheets/rss.xsl" media="screen"?><rss version="2.0" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:slash="http://purl.org/rss/1.0/modules/slash/" xmlns:wfw="http://wellformedweb.org/CommentAPI/"><channel><title>XN bit support on ARMv7 Cortex A15</title><link>https://community.arm.com/developer/tools-software/tools/f/armds-forum/1108/xn-bit-support-on-armv7-cortex-a15</link><description> </description><dc:language>en-US</dc:language><generator>Telligent Community 10</generator><item><title>RE: XN bit support on ARMv7 Cortex A15</title><link>https://community.arm.com/thread/3440?ContentTypeID=1</link><pubDate>Wed, 11 Sep 2013 11:08:36 GMT</pubDate><guid isPermaLink="false">dd9e70c8-6d3c-4c71-b136-2456382a7b5c:c2106e2b-4b5c-43d0-bea2-0e3b4ba1271f</guid><dc:creator>Peter Harris</dc:creator><description>&lt;div&gt;&lt;i&gt;Note: This was originally posted on 11th June 2013 at &lt;a href="http://forums.arm.com"&gt;http://forums.arm.com&lt;/a&gt;&lt;/i&gt;&lt;br /&gt;&lt;br /&gt;&lt;span&gt;Realize this is an old post, but I hit it with a Google search, so I thought worth posting &amp;quot;probable cause&amp;quot;.&lt;/span&gt;&lt;br /&gt;&lt;br /&gt;&lt;span&gt;I suspect your test case is incorrect. You mention you are pushing executable code onto the stack and sometimes getting a fault, and sometimes not. &lt;/span&gt;&lt;br /&gt;&lt;br /&gt;&lt;span&gt;ARMv7 does not include hardware memory coherency between I-cache and D-cache, so you are getting a cache coherency problem where you have written the code to the D cache, but the I cache is probably trying to execute the old data rather than your new code. What you are trying to do is invalid without manual cache operations to ensure I and D sides of the memory system see the same data values.&lt;/span&gt;&lt;br /&gt;&lt;br /&gt;&lt;span&gt;HTH, &lt;/span&gt;&lt;br /&gt;&lt;span&gt;Iso&lt;/span&gt;&lt;/div&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: XN bit support on ARMv7 Cortex A15</title><link>https://community.arm.com/thread/3438?ContentTypeID=1</link><pubDate>Wed, 11 Sep 2013 11:08:36 GMT</pubDate><guid isPermaLink="false">dd9e70c8-6d3c-4c71-b136-2456382a7b5c:784d7418-8410-46dc-9c6f-f942bc6af90a</guid><dc:creator>Peter Harris</dc:creator><description>&lt;div&gt;&lt;i&gt;Note: This was originally posted on 9th January 2013 at &lt;a href="http://forums.arm.com"&gt;http://forums.arm.com&lt;/a&gt;&lt;/i&gt;&lt;br /&gt;&lt;br /&gt;&lt;span&gt;I think the v6 and v7 page tables are (mostly) the same unless you are using the large physical address space, so yes the v6 XN should work fine for Cortex-A15.&lt;/span&gt;&lt;br /&gt;&lt;br /&gt;&lt;span&gt;HTH,&lt;/span&gt;&lt;br /&gt;&lt;span&gt;Iso&lt;/span&gt;&lt;/div&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: XN bit support on ARMv7 Cortex A15</title><link>https://community.arm.com/thread/3439?ContentTypeID=1</link><pubDate>Wed, 11 Sep 2013 11:08:36 GMT</pubDate><guid isPermaLink="false">dd9e70c8-6d3c-4c71-b136-2456382a7b5c:696fcd9f-9114-4452-b458-0900d95c346d</guid><dc:creator>taani E</dc:creator><description>&lt;div&gt;&lt;i&gt;Note: This was originally posted on 10th January 2013 at &lt;a href="http://forums.arm.com"&gt;http://forums.arm.com&lt;/a&gt;&lt;/i&gt;&lt;br /&gt;&lt;br /&gt;&lt;span&gt;To verify the XN bit support on Cortex A15. I executed the attached c test code.&lt;/span&gt;&lt;br /&gt;&lt;span&gt;&amp;#160;&amp;#160;&amp;#160;&amp;#160;&amp;#160; &lt;/span&gt;&lt;br /&gt;&lt;span&gt;I followed below steps to test XN bit support.&lt;/span&gt;&lt;br /&gt;&lt;br /&gt;&lt;span&gt;1. I compiled attached test program i.e exectest with &amp;quot;-z execstack&amp;quot;&amp;amp;#157;option (gcc -z execstack -o exectest exectest.c -lpthread)&lt;/span&gt;&lt;br /&gt;&lt;br /&gt;&lt;span&gt;2. I &lt;/span&gt;&lt;strong&gt;removed &lt;/strong&gt;&lt;span&gt;XN bit related code in ./arch/arm/mm/mmu.c and burned kernel on target.&lt;/span&gt;&lt;br /&gt;&lt;span&gt;&amp;#160;&amp;#160;&amp;#160;&amp;#160; &lt;/span&gt;&lt;strong&gt;Filename : arch/arm/mm/mmu.c&lt;/strong&gt;&lt;span&gt;Line:&amp;#160; 346&amp;#160;&amp;#160; &lt;/span&gt;&lt;br /&gt;&lt;span&gt;&amp;#160;&amp;#160;&amp;#160;&amp;#160;&amp;#160;&amp;#160;&amp;#160; if(cpu_is_xsc3() || (cpu_arch &amp;gt;= CPU_ARCH_ARMv6 &amp;amp;&amp;amp; (cr &amp;amp; CR_XP))){&lt;/span&gt;&lt;br /&gt;&lt;span&gt;&amp;#160;&amp;#160;&amp;#160;&amp;#160;&amp;#160;&amp;#160;&amp;#160; if (!cpu_is_xsc3()) {&lt;/span&gt;&lt;br /&gt;&lt;br /&gt;&lt;span&gt;&amp;#160; #if 0&lt;/span&gt;&lt;br /&gt;&lt;br /&gt;&lt;span&gt;&amp;#160;&amp;#160;&amp;#160;&amp;#160;&amp;#160;&amp;#160;&amp;#160;&amp;#160;&amp;#160;&amp;#160;&amp;#160;&amp;#160;&amp;#160;&amp;#160;&amp;#160;&amp;#160;&amp;#160;&amp;#160;&amp;#160;&amp;#160; /*&amp;#160; Mark device regions on ARMv6+ asexecute-never&lt;/span&gt;&lt;br /&gt;&lt;br /&gt;&lt;span&gt;&amp;#160;&amp;#160;&amp;#160;&amp;#160;&amp;#160;&amp;#160;&amp;#160;&amp;#160;&amp;#160;&amp;#160;&amp;#160;&amp;#160; * to prevent speculativeinstruction fetches. */&lt;/span&gt;&lt;br /&gt;&lt;br /&gt;&lt;span&gt;&amp;#160;&amp;#160;&amp;#160;&amp;#160;&amp;#160;&amp;#160;&amp;#160;&amp;#160;&amp;#160;&amp;#160;&amp;#160;&amp;#160;&amp;#160; mem_types[MT_DEVICE].prot_sect |= PMD_SECT_XN;&lt;/span&gt;&lt;br /&gt;&lt;br /&gt;&lt;span&gt;&amp;#160;&amp;#160;&amp;#160;&amp;#160;&amp;#160;&amp;#160;&amp;#160;&amp;#160;&amp;#160;&amp;#160;&amp;#160;&amp;#160;&amp;#160; mem_types[MT_DEVICE_NONSHARED].prot_sect |= PMD_SECT_XN;&lt;/span&gt;&lt;br /&gt;&lt;br /&gt;&lt;span&gt;&amp;#160;&amp;#160;&amp;#160;&amp;#160;&amp;#160;&amp;#160;&amp;#160;&amp;#160;&amp;#160;&amp;#160;&amp;#160;&amp;#160;&amp;#160; mem_types[MT_DEVICE_CACHED].prot_sect |= PMD_SECT_XN;&lt;/span&gt;&lt;br /&gt;&lt;br /&gt;&lt;span&gt;&amp;#160;&amp;#160;&amp;#160;&amp;#160;&amp;#160;&amp;#160;&amp;#160;&amp;#160;&amp;#160;&amp;#160;&amp;#160;&amp;#160;&amp;#160; mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_XN;&lt;/span&gt;&lt;br /&gt;&lt;br /&gt;&lt;span&gt;&amp;#160; #endif&lt;/span&gt;&lt;br /&gt;&lt;br /&gt;&lt;span&gt;&amp;#160;&amp;#160;&amp;#160;&amp;#160;&amp;#160;&amp;#160;&amp;#160;&amp;#160;&amp;#160;&amp;#160;&amp;#160;&amp;#160; }&lt;/span&gt;&lt;br /&gt;&lt;br /&gt;&lt;span&gt;&amp;#160;&amp;#160;&amp;#160;&amp;#160;&amp;#160; if (cpu_arch &amp;gt;= CPU_ARCH_ARMv7 &amp;amp;&amp;amp; (cr &amp;amp; CR_TRE)) {&lt;/span&gt;&lt;br /&gt;&lt;br /&gt;&lt;span&gt;3. Executed test program on target.&lt;/span&gt;&lt;br /&gt;&lt;br /&gt;&lt;strong&gt;4.&amp;#160;&amp;#160;&amp;#160; &lt;/strong&gt;&lt;strong&gt;I found some times successful execution with correct output and sometimes page fault.&lt;/strong&gt;&lt;br /&gt;&lt;br /&gt;&lt;span&gt;&amp;#160; As per my understanding this test program should always execute correctly and give correct output.&lt;/span&gt;&lt;br /&gt;&lt;br /&gt;&lt;span&gt;&amp;#160; If I skip step 2 (means not commenting the XN bit related code) then also I have got the same behavior.&lt;/span&gt;&lt;br /&gt;&lt;br /&gt;&lt;strong&gt;Please let me know how to verify XN bit support.&lt;/strong&gt;&lt;br /&gt;&lt;strong&gt;&lt;br /&gt;&lt;/strong&gt;&lt;br /&gt;&lt;strong&gt;&lt;br /&gt;&lt;/strong&gt;&lt;br /&gt;&lt;strong&gt;Thanks &amp;amp; Regards,&lt;br /&gt;&lt;/strong&gt;&lt;/div&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item></channel></rss>