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NIC-400 Interconnect generation issue
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NIC-400 Interconnect generation issue
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narendra kandimalla
over 7 years ago
Note: This was originally posted on 27th December 2012 at http://forums.arm.com
Hi ,
I am using NIC-400 for AXI 128x64 interconnect. 1-slave X 2-masters.
Read transactions with arsize=4,arlen(burst lenth)=16 and burst size=3 doesn't give any issues.
BUT below read scenario is giving issue..........
Scenario:- AXI Read Transaction, Incrementing Burst with Burst Length 1.
Data for "arsize = 3". --Transaction Size = 8Bytes.
That means we are requesting 64-byte data from master side. In the simulation waveforms I can see a valid 64-bit data & 64-bit Zeros as valid next data each time.
In waveforms i can see XBAR selecting both lower 64-bit & higher 64-bit data of each 128-bit data it receives from slave.which its transfers as 2-valid data transactions to master.
During this process its missing to transfer another valid data it requested master(in this place Its transfering Valid ZERO data).
Is it The issue with XBAR generation?
Thanks,
Narendra
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Offline
narendra kandimalla
over 7 years ago
Note: This was originally posted on 27th December 2012 at
http://forums.arm.com
I have one more concern regarding AXI-Slave input coming to XBAR.
incase of 128X64 bit (128-bit slave & 64-bit master) If we are requesting a transaction of
ARSIZE=3 means 64-bit data
ARLEN=0
ARBURST=1 means incremental burst.
My understanding is that slave should place 64-bit data in MSB & LSB positions of 128-input to XBAR alternatively in consecutive transfers.
Is That correct
or
Any other control signals(like arprot etc) will effect the postion of 64-bit data from AXI slave to XBAR ?
Thanks,
Narendra
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Offline
narendra kandimalla
over 7 years ago
Note: This was originally posted on 27th December 2012 at
http://forums.arm.com
I have one more concern regarding AXI-Slave input coming to XBAR.
incase of 128X64 bit (128-bit slave & 64-bit master) If we are requesting a transaction of
ARSIZE=3 means 64-bit data
ARLEN=0
ARBURST=1 means incremental burst.
My understanding is that slave should place 64-bit data in MSB & LSB positions of 128-input to XBAR alternatively in consecutive transfers.
Is That correct
or
Any other control signals(like arprot etc) will effect the postion of 64-bit data from AXI slave to XBAR ?
Thanks,
Narendra
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