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Memory alignment while using LDR instruction in cortex A9
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Memory alignment while using LDR instruction in cortex A9
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ANGEL MARY NATHAN
over 7 years ago
Note: This was originally posted on 3rd August 2012 at http://forums.arm.com
Hi,
I am facing some problem while trying to load a 32 bit value into a register by using LDR R0 [R1] where R1 is a pointer to a memory location having some value.
when i use the LDR instruction 3bytes are fetched from the location pointed by R1 and the 4th byte is 1byte before the loacation pointed by R1.
I am working on ARM Cortex A9 simulator.
Is it anything related to memory alignment?
How do i solve this?
Thanks in advance
Angel
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