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PL390 GIC Interrupt Grouping
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Stefan Kalkowski
over 7 years ago
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Martin Weidmann
over 7 years ago
Note: This was originally posted on 25th July 2012 at
http://forums.arm.com
Do you really mean the PL390, or the integrated IC in the MPCore? Not that it matters too much at this point.
I think this is a GICv1 vs GICv2 spec thing which I've hit in the past. In GICv2 the secure copy of the GICD_CTLR has enable bits for group 0 and 1. In GICv1 the secure GICD_CTRL is _only_ required to have the group 0 enable bit, it is IMPLEMENTATION DEFINED whether bit 1 is the group 1 enable. :-( The PL390/GIC-390 (which is GICv1) does not implement this bit.
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Martin Weidmann
over 7 years ago
Note: This was originally posted on 25th July 2012 at
http://forums.arm.com
Do you really mean the PL390, or the integrated IC in the MPCore? Not that it matters too much at this point.
I think this is a GICv1 vs GICv2 spec thing which I've hit in the past. In GICv2 the secure copy of the GICD_CTLR has enable bits for group 0 and 1. In GICv1 the secure GICD_CTRL is _only_ required to have the group 0 enable bit, it is IMPLEMENTATION DEFINED whether bit 1 is the group 1 enable. :-( The PL390/GIC-390 (which is GICv1) does not implement this bit.
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