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<?xml-stylesheet type="text/xsl" href="https://community.arm.com/utility/feedstylesheets/rss.xsl" media="screen"?><rss version="2.0" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:slash="http://purl.org/rss/1.0/modules/slash/" xmlns:wfw="http://wellformedweb.org/CommentAPI/"><channel><title>Compiler option to generate CPU log file</title><link>https://community.arm.com/developer/tools-software/tools/f/arm-compilers-forum/47996/compiler-option-to-generate-cpu-log-file</link><description> Hi, 
 We are using Cortex-M0+ embedded in our hardware design and would like to simulate the firmware along with the micro and the rest of the hardware using Synopsys Verdi HW/SW Debugger which works together with Eclipse. The debugger requires an .fsdb</description><dc:language>en-US</dc:language><generator>Telligent Community 10</generator><item><title>RE: Compiler option to generate CPU log file</title><link>https://community.arm.com/thread/168578?ContentTypeID=1</link><pubDate>Tue, 10 Nov 2020 17:52:16 GMT</pubDate><guid isPermaLink="false">dd9e70c8-6d3c-4c71-b136-2456382a7b5c:c7cd9d30-711d-4f6b-a89b-3c5fc06fd7fd</guid><dc:creator>Nazar</dc:creator><description>&lt;p&gt;Hi Jason,&lt;/p&gt;
&lt;p&gt;It would be great to discuss this process in more detail. How do I jump into private messaging?&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: Compiler option to generate CPU log file</title><link>https://community.arm.com/thread/168577?ContentTypeID=1</link><pubDate>Tue, 10 Nov 2020 17:34:23 GMT</pubDate><guid isPermaLink="false">dd9e70c8-6d3c-4c71-b136-2456382a7b5c:9ae87e83-4dbd-49a9-9a02-b029f2557deb</guid><dc:creator>Jason Andrews</dc:creator><description>&lt;p&gt;Hi Nazar,&amp;nbsp;&lt;/p&gt;
&lt;p&gt;Looks like there is some confusion here. We don&amp;#39;t know exactly how the Synopsys tool works, but can try to help.&lt;/p&gt;
&lt;p&gt;You have the ELF file as your compiled software. The FSDB file is generated by the Verilog simulation. It contains information about the hardware design, signals, registers, memory, etc.&lt;/p&gt;
&lt;p&gt;The cpu.log is unclear. The Cortex-M0+ Verilog simulation has a feature to generate a file called a &amp;quot;tarmac file&amp;quot; which has information similar to what you showed, but the format is not exactly the same so maybe this is a file generated by Synopsys, not sure. The tarmac file is a text file which is created by the simulation which contains the instructions executed, the memory loads/stores, register changes, etc.&lt;/p&gt;
&lt;p&gt;I can guess the Synopsys tool uses the FSDB file to find things like the program counter and map the executed instructions back to your source code in eclipse so you can see the flow of execution. If you need more info about how the tarmac is generated or other questions about the simulation of the Cortex-M0+ please let us know.&lt;/p&gt;
&lt;p&gt;Feel free to send me a private message if you want to have a meeting.&lt;/p&gt;
&lt;p&gt;Thanks, Jason&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: Compiler option to generate CPU log file</title><link>https://community.arm.com/thread/168571?ContentTypeID=1</link><pubDate>Tue, 10 Nov 2020 14:37:08 GMT</pubDate><guid isPermaLink="false">dd9e70c8-6d3c-4c71-b136-2456382a7b5c:d8a436fa-c6bd-4acb-9cef-fb63f1555f8d</guid><dc:creator>Nazar</dc:creator><description>&lt;p&gt;Ronan, I contacted Synopsys and they directed me back to ARM (expected). It does&amp;nbsp;appear&amp;nbsp;that this file is generated by the Synopsys tools, but the User Guide says the following: &amp;quot;Enable log file dumping in the design before starting simulation. See CPU Vendor documentation for details.&amp;quot; - not many clues.&lt;br /&gt;Maybe my question should be moved to a more related forum thread?&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: Compiler option to generate CPU log file</title><link>https://community.arm.com/thread/168544?ContentTypeID=1</link><pubDate>Mon, 09 Nov 2020 15:38:58 GMT</pubDate><guid isPermaLink="false">dd9e70c8-6d3c-4c71-b136-2456382a7b5c:da519e28-fec5-49f8-b5ec-b672be038bff</guid><dc:creator>Nazar</dc:creator><description>&lt;p&gt;Hi Ronan,&lt;/p&gt;
&lt;p&gt;I thought so too, but I was mislead by Synopsys User guide saying &amp;quot;The CPU log file generated from the design (executing embedded C code) is used as an input by Verdi HW/SW Debug Solution.&lt;strong&gt; For details on generating this file, refer to your CPU vendor instructions.&lt;/strong&gt;&amp;quot;&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: Compiler option to generate CPU log file</title><link>https://community.arm.com/thread/168524?ContentTypeID=1</link><pubDate>Mon, 09 Nov 2020 01:01:04 GMT</pubDate><guid isPermaLink="false">dd9e70c8-6d3c-4c71-b136-2456382a7b5c:cbd755d0-ff35-4701-a12e-092f1590fe1b</guid><dc:creator>Ronan Synnott</dc:creator><description>&lt;p&gt;Hi Nazar,&lt;/p&gt;
&lt;p&gt;This appears to be Tarmac trace (specifically Register trace)&lt;br /&gt;&lt;a href="https://developer.arm.com/documentation/dui0532/c/tarmac-trace-file-format"&gt;developer.arm.com/.../tarmac-trace-file-format&lt;/a&gt;&lt;/p&gt;
&lt;p&gt;This is an output from the execution environment, not the compiler - you should consult with Synopsys on how to generate this with your setup.&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item></channel></rss>