We are using Cortex-M0+ embedded in our hardware design and would like to simulate the firmware along with the micro and the rest of the hardware using Synopsys Verdi HW/SW Debugger which works together with Eclipse. The debugger requires an .fsdb file which can be generated from the .elf file and cpu.log file. Both, I assume can be generated during compilation. Currently only the .elf file is being generated when using this command:
Is there a specific compile option to enable "cpu.log" file generation? I do not know how ARM referrers to this file, but the content of it should be something like: R CPSR 000001d3 10245 ns IE 00000000 [e59ff018] MR4 00000020 0000003c 10975 ns IE 0000003c [ea000011] 11445 ns IE 00000088 [e3a00000] R R0 00000000 11445 ns IE 0000008c [e3a01000] R R1 00000000 11445 ns IE 00000090 [e3a02000] R R2 00000000
R CPSR 000001d3
10245 ns IE 00000000 [e59ff018]
MR4 00000020 0000003c
10975 ns IE 0000003c [ea000011]
11445 ns IE 00000088 [e3a00000]
R R0 00000000
11445 ns IE 0000008c [e3a01000]
R R1 00000000
11445 ns IE 00000090 [e3a02000]
R R2 00000000
Thank you for your help.
This appears to be Tarmac trace (specifically Register trace)developer.arm.com/.../tarmac-trace-file-format
This is an output from the execution environment, not the compiler - you should consult with Synopsys on how to generate this with your setup.
Ronan, I contacted Synopsys and they directed me back to ARM (expected). It does appear that this file is generated by the Synopsys tools, but the User Guide says the following: "Enable log file dumping in the design before starting simulation. See CPU Vendor documentation for details." - not many clues.Maybe my question should be moved to a more related forum thread?
Looks like there is some confusion here. We don't know exactly how the Synopsys tool works, but can try to help.
You have the ELF file as your compiled software. The FSDB file is generated by the Verilog simulation. It contains information about the hardware design, signals, registers, memory, etc.
The cpu.log is unclear. The Cortex-M0+ Verilog simulation has a feature to generate a file called a "tarmac file" which has information similar to what you showed, but the format is not exactly the same so maybe this is a file generated by Synopsys, not sure. The tarmac file is a text file which is created by the simulation which contains the instructions executed, the memory loads/stores, register changes, etc.
I can guess the Synopsys tool uses the FSDB file to find things like the program counter and map the executed instructions back to your source code in eclipse so you can see the flow of execution. If you need more info about how the tarmac is generated or other questions about the simulation of the Cortex-M0+ please let us know.
Feel free to send me a private message if you want to have a meeting.
It would be great to discuss this process in more detail. How do I jump into private messaging?
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