I am attempting to run an in house benchmark on a cycle accurate model of the ARM Cortex R52, in a baremetal setup. I compiled and built my benchmark using GCC 7.2.1 - gcc version 7.2.1 20170904 (release) [ARM/embedded-7-branch revision 255204] (GNU Tools for Arm Embedded Processors 7-2017-q4-major. I am using newlib and passing -specs=nosys.specs to the linker. I have some basic startup code that sets up the vector table for exceptions and initialises the caches, TCMs etc.
Once code execution gets to __start (or _mainCRTStartup) (in crt.o), an 'Illegal exception return' occurs when executing an instruction after the following one:
msr CPSR_c, #209 ; 0xd1
The above instruction is part of a section where the SPs for each mode are being set up. The instruction attempts to change to FIQ mode. From what I could understand from the ARMv8 and ARMv8-R architecture manuals, attempting to modify CPSR's mode bits, when in Hypervisor mode, is illegal. Even the Cortex R52 manual recommends a slightly different method of changing from EL2 (Hyp.) to EL1(FIQ etc.). As per the R52 manual, the processor is in Hypervisor mode out of reset.
My question is whether this is a bug or am I using a wrong version of newlib. Am I supposed to switch to an EL1 mode prior to jumping to __start? If yes, does that mean I need to set up the SP and (also stack limit?) for Hypervisor mode on my own?
The title could be a bit misleading. I meant I get an 'Illegal Exception Return to AArch32 state' exception, not that the exception is illegal itself.
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