The ARM® Cortex®-R52 processor is the most advanced processor for functional safety and the first implementation of the ARMv8-R architecture. Along with the announcement of the Cortex-R52, ARM offers a number of development tools to help partners speed up their path to market. This is especially helpful for a new architecture which highlights software separation for safety and security. This article summarizes the available tools and explains what’s new for the Cortex-R52.
The Cortex-R52 is the first ARMv8-R processor. ARMv8-R brings real-time virtualization to Cortex-R in the form of a new privilege Level, EL-2, which provides exclusive access to a second stage Memory Protection Unit (MPU). This enables bare metal hypervisors to maintain software separation for multiple operating systems and tasks.
Many partners will be interested in the differences between the Cortex-R52 and previous designs, such as the Cortex-R5 and Cortex-R7. The Cortex-R52 evolves the Cortex-R5 microarchitecture by providing fast, deterministic interrupt response and low latency at a performance level which is better than Cortex-R7 on some real-time workloads. Cortex-R52 also offers a dedicated, read-only, low-latency flash interface which conforms to the AXI4 specification.
ARM Fast Models and Cycle Models enable virtual prototyping for software partners to develop solutions for the new Cortex-R52 before silicon is available.
DS-5 Development Studio is the ARM tool suite for embedded C/C++ software development on any ARM-based SoC. DS-5 features the ARM Compiler, DS-5 Debugger, and Streamline system profiler. Also included is a comprehensive and intuitive IDE, based on the popular and widely-used Eclipse platform.
The DS-5 Debugger is developed in close co-operation with ARM processor and subsystem IP. DS-5 is used inside ARM as part of the development and verification cycle and is extensively tested against models, early FPGA implementations and (as soon as it is available) silicon. The DS-5 Debugger provides early-access debug and trace support to ARM lead partners working with leading-edge IP. This enables mature, stable, validated debug and trace support for Cortex-R52 to be included in the upcoming DS-5 release, version 5.26.
ARM Compiler 6 is the latest compilation toolchain for the ARM architecture, and is included in the DS-5 Development Studio. ARM Compiler 6 brings together the modern LLVM compiler infrastructure and the highly optimized ARM C libraries to produce performance and power optimized embedded software for the ARM architecture.
ARM Compiler 6 is developed closely with ARM IP and provides early-access support to lead partners. As with core support in all compilers code generation, performance, and code size improve over time, with improvements driven by experience and feedback from real-world use-cases. The upcoming release of ARM Compiler 6, version 6.6, will feature full support of link time optimization and enhanced instruction scheduling support, giving an improvement of nearly 10 percent for Cortex-R52 in key benchmark scores. Combined with significant improvements in code size, ARM Compiler 6 is a comprehensive choice for the Cortex-R52.
Cortex-R52 provides a compelling opportunity for users to migrate from ARM Compiler 5 to ARM Compiler 6. The ARM Compiler migration and compatibility guide aids the evaluation process by comparing the command line options, source code differences, assembly syntax, and other topics of interest.
If existing code needs to be updated from ARM Compiler 5 to ARM Compiler 6, the first step is to get the code to successfully compile. This generally takes a combination of Makefile changes to invoke the new compiler as well as source code adaptations.
First, compiler invocation needs to be switched from armcc to armclang. Other tools like armasm and armlink are included in ARM Compiler 6 and can continue to be used.
For example, when changing from Cortex-R7 to Cortex-R52 a few compiler command line option changes will be required:
ARM Compiler 5
ARM Compiler 6
--target= armv8r-arm-none-eabi –mcpu=cortex-r52
-Os / -Oz
-Onum (default is 2)
-Onum (default is 0)
The migration guide provides further details related to specific switches, but these are the basics to get going. Some compiler switches may need to be removed because they are specific to armcc; for example, --apcs /interwork and --no_inline are not needed with armclang and can be removed.
Fast Models are an accurate, flexible programmer's view models of ARM IP, allowing you to develop software such as drivers, firmware, operating systems and applications prior to silicon availability. They allow full control over the simulation, including profiling, debug and trace. Fast Models can be exported to SystemC, allowing integration into the wider SoC design process.
Fast Models typical use cases:
The Fast Model for the Cortex-R52 is being released in late September as part of Fast Models 10.1.
Cycle models are compiled directly from ARM RTL and retain complete functional accuracy. This enables users to confidently make architecture decisions, optimize performance or develop bare metal software. Cycle Models run in SoC Designer or any SystemC simulator, including the Accellera reference simulator and simulators from EDA partners.
Cycle Models typical use cases:
The Cortex-R52 SystemC Cycle Model supports a number of features which help with performance analysis:
The Cycle Model for the Cortex-R52 is being released in late September and will be available on ARM IP Exchange.
Does Cortex-R52 require DS-5 Ultimate Edition?
Yes, DS-5 Ultimate Edition is required for debugging with Cortex-R52.
What are the switches for ARM Compiler 6 to select Cortex-R52?
For ARM Compiler 6.6 use the armclang switches: --target=armv8r-arm-none-eabi -mcpu=cortex-r52
For ARM Compiler 6.5 use the armclang switches: --target=armv8r-arm-none-eabi -mcpu=kite
Can DS-5 be used for software debugging with a simulation model?
Yes, before silicon is available DS-5 can be used to develop and debug software using the Cortex-R52 Fast Model. The Fast Model can be used for functional software development, checking compliance with the ARMv8-R architecture, and software optimization. DS-5 with the Fast Model makes an ideal development environment for hypervisors, schedulers, real-time operating systems, and communication stacks.
Is there a model available for verification which works in EDA simulators?
Yes, the Cortex-R52 Cycle Model can be used in any EDA simulator. It has a SystemC wrapper which can be instantiated in a Verilog or VHDL design. It provides 100% cycle accuracy.
Is there a way to run benchmarks to compare Cortex-R52 to another core such as Cortex-R5 or Cortex-R7?
Yes, the Cortex-R52 Cycle Model instruments the Performance Monitor Unit (PMU) and provides a tarmac trace to run benchmarks and evaluate performance.
The Cortex-R52 CPU model doesn’t seem to start running after reset, is the model broken?
No, the most common cause is the CPUHALTx input is asserted and stopping the core from running.
Do Cortex-R52 models allow simulation of booting from TCM?
Yes, both the Fast Model and the Cycle Model can boot from TCM. The CFGTCMBOOTx enables the ATCM from reset on the Cycle Model and the Fast Model provides the tcm.a.enable parameter to do the same thing.
A full suite of development tools is available for the Cortex-R52, which enables developers to do more, earlier with the most advanced ARM processor for functional safety and learn about the ARMv8-R architecture. Please refer to developer.arm.com for more information on ARM Development Tools.
Following up on the article, the Fast Model and the Cycle Model for the Cortex-R52 are now available.