I have a question about how to make Ethos-U NPU work on a ARM Cortex-A + Cortex-M processor. First, I found ethos-u-linux-driver-stack and ethos-u-core-software on https://git.mlplatform.org/.
1. I know ethos-u-linux-driver-stack is Ethos-U kernel driver. Should it be integrated into the Linux OS running on Cortex-A or be integrated into the Linux OS running on Cortex-M? I am nor clear about which core it need to perform on.
2. For ethos-u-core-software, how to run it? I did't find the detail steps to run it. Does it run on NPU or any core?
3. Except the above two repos, is there any other repo necessory to make Ethos-U NPU work on an ARM Cortex-A + Cortex-M processor?
Thanks for your suggestion in advance.
Recently I have some hardware questions about ethos-u65. Could you give me some guide?
For field shram_size in CONFIG register, I see there are two values, SHRAM_48kB and SHRAM_96kB.
For DMA controller, I see there are several channels.
For Arm AMBA 5 AXI interfaces, there are two read/write master M0 and M1.
I thought I had responded to this question, but I can't find my answer in the thread.
The SHRAM is built into the NPU and the size can't be changed by software. The memory is typically used for storage of weights, biases and temporary data. This is a small memory that will not fit a network like ssd mobilenet. Instead small portions of the weighs and biases are copied to the SHRAM as they are needed.
There are 8 "logical memory channels". Which logical channel that is used for what data (ifm, ofm, weights, biases etc) is coded in the command stream by Vela. The driver maps the logical channels to the physical DMA interfaces (M0 and M1) in the region config registers.
Consequently which DMA interface that is used depends both on Vela and the driver. Now this is subject to change, but as of today with the default settings in Vela and the driver, the command stream, weights and biases will go over M1, and all other data over M0. This allows the TFLu model (command stream, weights and biases) to be moved from fast memory (SRAM) to slower memory (flash or DRAM) without congesting the M0 interface.
Kristofer, please help to confirm my below comments.
1. The fast memory (SRAM) you mentioned in "This allows the TFLu model (command stream, weights and biases) to be moved from fast memory (SRAM) to slower memory (flash or DRAM) without congesting the M0 interface." is the SHRAM built into the NPU, right?
2. Now, the current process is SHRAM <-> DMA & M1 or M0 <-> slower memory (flash or DRAM), right?
Maybe I didn't understand your last sentence clearly.
The TFLu has two buffer, model and arena. For optimal performance both the model and the arena should be placed in SRAM (or similar memory technology), however SRAM is expensive and at the cost of performance the model could be moved to DRAM or flash.
Kristofer, I want to set the particular SRAM and DRAM address for U65 on our processor, how should I do?
I am not sure what you mean with setting the SRAM and DRAM address for U65. Could you please elaborate a bit more on what problem you have?
If you for example wonder about how to place the model and arena buffers in memory, then perhaps this information might help you.
Running an inference on the TFLu framework requires three memory regions.
For the tests we have upstreamed to MLPlatform we have defined two additional buffers.
Please have a look at the baremetal example application. Each buffer is named with a section attribute.
The section attributes are placed in memory by the scatter file (ArmClang) or linker script (GCC). To change where the buffers are placed in memory you need to edit the scatter file or linker script.
Hi, Kristofer, thanks for your sharing. I have a reference about the codes on corstone-300. It seems ifm, model(weights, biases and the Ethos-U command stream), ofm are located in SRAM. If ETHOSU_FAST_MEMORY_SIZE is defined, tensor arena will be located in SRAM, or else it will be located in DDR. I think ETHOSU_FAST_MEMORY_SIZE means whether there is a fast memory, such as SRAM. Please correct me, if there is anything wrong.
Actually, in my current codes, ifm, model, ofm and tensor arena are all located in DDR. I think only AXI M1 inference is used, because M1 is connected to DDR, M0 is connected to fast memory (on-chip SRAM) in our system. So I want to know whether I need to change Vela tool or driver to make this case work. For example, model is located at DDR, and AXI M1 is used, should I make some configuration in Vela tool or driver for it?
Moreover, as there is fast memory in our system, should I locate tensor arena in fast memory (on-chip SRAM)? I think the fast memory is not large enough for the model, such as mobilenet v1.
Hi, Kristofer, except the above questions, I also have some confusion about two hardware registers.
The first register is REGIONCFG. What does the region mean? What data should be located at region 0-7? For each region, is it needed to config the region connects to AXI0 or AXI1?
The second register is BASEPx. According to the codes, the address of weight, input tensor and other buffers are written to BASEPx. Is there a rule to put the specific buffer address to the specific BASEPx? For example, BASEP0 is necessary to write weight buffer address.
Please help to give me some guide.
As mentioned in previous comments there there are two TFLu buffers - model and arena - that need to be placed in memory. For a system with SRAM and DRAM we have three combinations that make sense.
Vela allocates a buffer inside of the arena. This buffer contains temporary data that the NPU will access frequently, and should for optimal performance be placed in SRAM.
However, for alternative 3 the arena will be placed in DRAM. For this option Vela can be configured to split the temporary data into an "arena buffer" and a "fast memory buffer". The Ethos-U will redirect the "fast memory buffer" to a memory area in SRAM.
The fast memory feature is a bit complicated and requires synchronized changes in several places:
Vela takes a tflite file as input, and produces another optimized tflite file as output. During the optimization phase Vela controls in which input tensors data is placed, like this:
The Ethos-U NPU driver writes the address of the command stream to the QBASE register. The addresses of input tensors 2-4 are written to the BASEP<nr> registers. If spilling has been enabled, then the driver will override the 'fast' tensor address before the BASEP<nr> register is written.
The Ethos-U NPU has two AXI interfaces, M0 and M1. The REGIONCFG register controls over which AXI interface the base pointers are routed to.
For example, with current Vela implementation weights and biases are accessed over base pointer 0. In the region config you can control if base pointer 0 should use M0 or M1.
The default region config is defined here. Please note that AXI0 and AXI1 are routed to M0, and AXI2 and AXI3 to M1.