Could arm-none-eabi-gcc split a LDRD(64bit load) from an unaligned address into two LDR?

Hi, experts,

When testing codes below on Cortex-M4F. It seems armcc(Keil) handles the unaligned memory access very well and the dword load is compiled into two LDR instructions. But gcc generates one single LDRD from the unaligned address which triggers unaligned mem fault. Could gcc behave like armcc and use two LDR instead of one LDRD when it's unaligned?

for (i = 0; i < 4; i++)
{
    address = 0x20001000 + i;

    bword = *(uint8_t *)address;
    hword = *(uint16_t *)(address+1);
    word = *(uint32_t *)address;
    dword = *(uint64_t *)(address+2);

    sum += bword + hword + word + dword;
}

Thanks.

Best regards.

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