I am trying to use the ETM on iMX53 qsb, which contains a Cortex-A8 processor. In the board, the trace result of the ETM is outputted to both ETB and TPIU via an ATB replicator, looks like the following figure,
I am going to enable the ETM and read the trace result from the ETM. Thus, I followed the example in http://infocenter.arm.com/help/topic/com.arm.doc.ihi0014q/IHI0014Q_etm_architecture_spec.pdf section 3.5.7 to configure the ETM, and enabled the ETB by setting the ETB control register. In this board, there is no funnel between the ETB and ETM, and also no programmable registers for the replicator, so I guess my configuration should work. However, it turns out that I cannot get any output from the ETB. I am not sure what has happened, and try to find out whether the ETM is working. Unlike the Trace Status Register in the ETM v4 specification, it seems that there is no register showing whether the trace unit is idle or not in the ETM v3.3 specification. The value of ETMSR register is 0x8 after i enabled the ETM, but i am not sure whether it indicates the ETM is working or not.
Is there anyone has experience on ETM v3.3 and know what is happening?
Appreciate for any help and discussion.
For more details, I configure the registers in the following steps,
1. Unlock the CoreSight lock of ETB
2. Set the TraceCaptEn bit in the CTL register of ETB
3. Lock the CoreSight lock of ETB
4. Unlock the CoreSight lock of ETM
5. Unlock the OS lock of ETM
6. Set the Programming bit in ETMCR
7. Clear the power down bit in ETMCR
8. Set ETMCR to 0x50001548
9. Set ETMTECR1 to 0x1000000
10. Set ETMTECR2 to 0x0
11. Set ETMTEEVR to 0x6F
12. Set ETMEXTINSELR to 0x0
13. Clear the Programming bit in ETMCR
14. Lock the OS lock of ETM
15. Do something in the OS
16. Unlock the CoreSight lock of ETB
17. Set the StopFl bit in the ETB FFCR register
18. Set the FOnMan bit in the ETB FFCR register
19. Wait until the AcqComp bit in the ETB STS register is set
20. Read from the ETB RRD register until getting 0xFFFFFFFF
21. Clear the TraceCaptEn bit in the ETB CTL register
22. Unlock the CoreSight lock of ETM
23. Set the Programming bit in ETMCR
24. Set the power down bit in ETMCR
The issue is that the first read in step 20 directly gives me 0xFFFFFFFF which means there is no trace stream in the ETB.
I solved the problem. Actually, i used the wrong way to access the ETB. After comparing with the ETB driver of Linux kernel, I finally get the trace result.
To make all the configurations, using code, did you use pointers?