Hello,
I have used DS-5+DSTREAM to connect to the A57/A53 big.LITTLE clusters on my Juno dev board. I use the startup_ARMv8_GICv2 example project included with DS-5 as the bare-metal image to run.
When I navigate to the cache view window in DS-5, I can see into the L2 on the A57, but not on the A53. Attached are screenshots showing this behavior.
Is this intentional? Is it possible to see into the A53s' L2? If so, how?
Thank you,
Marc
Hi Marc,
Which version of DS-5 are you using?
Ta,
Matt
Hi Matt,
Thanks for the quick reply. I'm using:
Version: 5.25.0
Build number: 5250010
EDIT: I just saw a new version of DS-5 was released a few days ago. I've updated to:
Version: 5.26.0
Build number: 5260008
But the functionality is still missing.
Oops, might have lead you on a merry path there, when I clicked the A57 image I saw the same thing (no L2 present) which was odd.
The issue here is that isn't any access to the L2 RAMs on Cortex-A53. This isn't a limitation of DS-5 - it's a limitation of the Cortex-A53.
is this limitation of the Cortex-A53 documented anywhere? I couldn't find it.
It's not documented because it doesn't exist.. most companies tend not to dedicate chapters of technical reference manuals on discussion of non-existent features.
You might note that the Cortex-A53 TRM does mention internal RAM access for the L1 cache subsystem, but not for L2. Unfortunately that's a big a clue as you'll get..
(To clarify, the poster above is not me.)
I am disappointed to hear that I cannot debug the L2 cache on the A53.
Obviously there is no expectation to dedicate chapters to non-existent features, but I would have really appreciated knowing about this before purchasing the DSTREAM. Perhaps it was my own fault for not doing enough due diligence, but I was expecting the official ARM debugger to let me debug everything the official ARMv8 dev platform shipped with. I just wish this missing functionality was made clear instead of leaving just a clue...
Thanks for your help.
I also think this could be better documented. Specially because the Juno Board SoC comes with two clusters: A53 and A57. While I can look into the A57's L2 cache, I can't look into A53's cache. This differences could be better marked.
Leandro.
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