about determining cold boot, warm boot

many times, can't understand it even though I read it :)

In https://chromium.googlesource.com/external/github.com/ARM-software/arm-trusted-firmware/+/v0.4-rc1/docs/firmware-design.md#bl1, it says,

Whenever a CPU is released from reset, BL1 needs to distinguish between a warm boot and a cold boot. This is done using a platform-specific mechanism. The ARM FVPs implement a simple power controller at 0x1c100000. The PSYS register (0x10) is used to distinguish between a cold and warm boot. This information is contained in the PSYS.WK[25:24] field. Additionally, a per-CPU mailbox is maintained in trusted DRAM (0x00600000), to which BL1 writes an entrypoint. Each CPU jumps to this entrypoint upon warm boot. During cold boot, BL1 places the secondary CPUs in a safe platform-specific state while the primary CPU executes the remaining cold boot path as described in the following sections.

is the PSYS register (at 0x10) of the 'simple power controller at 0x1c100000'? (I guess so, it would have been better if it said 'The PSYS register (0x10) of the controller ~')

and how is the PSYS.WK[25:24] determined? looks like it is some preset value by hard reset but is not reset by software reset. is it correct? 

also, it said there is a 'per-cpu' mailbox at 0x00600000. then all the cpu jumps to the address written in 0x00600000? how is it called 'per-cpu' mailbox? (I would use 0x00600000 for core 0, 0x00600008 for core 1, etc..)

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