I am developing the model of a block for a virtual platform using Lisa+.
I know how to trigger a behaviour through read and write accesses on the PVBus. However I don't know how to do that for a slave port <signal>.
Can you please explain me how to do that? I haven't been able to find anything in the documentation.
I would really appreciate if you provide me with some simple example code.
Thank you in advance.
Are you using Fast Models to do this? If so, take a look at the signalogger component. This has examples of how to do this on both slave and master ports. In summary signal_master_port.setValue(sg::Signal::Set); will set the signal and signal_master_port.setValue(sg::Signal::Clear); will clear it.
thank you for the explanation. Yes, I'm using Fast Models.
I've been able to implement it now. The idea of having a setValue behaviour for implementing the sensitivity of a slave port was a bit misleading for me, but now I have understood.
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