questions about vttbr_el2

Hello,

In the ARM Architecture Reference Manual ARMv8, for ARMv8-A architecture profile, there's a description about vttbr_el2: " Register bits[47:x] hold bits[47:x] of the stage 1 translation table base address" . I am a little confused, as far as I know , the vttbr_el2 register hold the stage 2 page table base address, so what's the meaning of " stage 1 translation table base address"? 

Also, I tired to open the 2 stage paging in my system. I setup the 2 stage page table at  physical address(0x20000000), and set the vttbr_el2 to this value.However, I got a Data Abort (code: 000101) which means a level 1 translation fault in stage 2 translation. So what's the correct usage of  vttbr_el2? 

I am using cortex-a53 and here's the related register value I set:

HCR: 0x80000001

VTCR_EL2: 0x80023558

VTTBR_EL2: 0x20000000

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  • I am a little confused, as far as I know , the vttbr_el2 register hold the stage 2 page table base address, so what's the meaning of

    Yes, unfortunately that looks like a docs error, I raise it with the docs team.

    On the abort, I don't see anything obviously wrong with the register values.  What values do you get in ESR_EL2 and HPFAR_EL2, and what have you populated the translation table with?

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  • I am a little confused, as far as I know , the vttbr_el2 register hold the stage 2 page table base address, so what's the meaning of

    Yes, unfortunately that looks like a docs error, I raise it with the docs team.

    On the abort, I don't see anything obviously wrong with the register values.  What values do you get in ESR_EL2 and HPFAR_EL2, and what have you populated the translation table with?

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