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PMU CP15 on AARCH64 - Cortex a-53 - Assembly Error on MRC-MCR

br-dev

Hi,

I am trying to compile PMU Cycle Counter  as per  the code available in this blog PMU Enable on a RPI3 B+ using Suse 64 bits Aarch 64 4.12.14-lp150.12.28-default.

I have the Assembly error on each MRC or MCR instructions. In the ARM i have the feeling that instructions and implementations are different

/tmp/ccQtUeOs.s: Assembler messages:
/tmp/ccQtUeOs.s:41: Error: unknown mnemonic `mrc' -- `mrc p15,0,x0,c9,c14,0'
/tmp/ccQtUeOs.s:55: Error: unknown mnemonic `mcr' -- `mcr p15,0,x0,c9,c14,0'
/tmp/ccQtUeOs.s:100: Error: unknown mnemonic `mrc' -- `mrc p15,0,x19,c9,c14,0'
/tmp/ccQtUeOs.s:120: Error: unknown mnemonic `mcr' -- `mcr p15,0,x19,c9,c14,0'

To read the CCNTR,  THE Aarch32 was  asm volatile("MRC p15, 0, %0, c9, c13, 0 \t\n" : "=r"(cycle_count));  and i need to translate too into

I cannot find the equivalence from Aarch32 to Aarch64 to read PMCCNTR_EL0 and so to enable the module kernel and read the counter. Did you find someone who fix it ? Unfortunatly I found nothing ready to go for dummies (like i am on this topic) !

Thanks regards


Architecture:        aarch64
Byte Order:          Little Endian
CPU(s):              4
On-line CPU(s) list: 0-3
Thread(s) per core:  1
Core(s) per socket:  4
Socket(s):           1
NUMA node(s):        1
Model:               4
BogoMIPS:            38.40
NUMA node0 CPU(s):   0-3
Flags:               fp asimd evtstrm crc32 cpuid