Cortex-A35 Counter-timer Physical Count register (CNTPCT_EL0) always reads zero

Counter-timer Physical Count register CNTPCT_EL0 always reads zero on FVP_Base_Cortex-A35x1.

I expect the value of this register to change over time.

I set $CNTFRQ_EL0=35000000, and $CNTP_CTL_EL0=5.

What is the possible reasons, and how is there any configuration I need make to enable this counter? Thanks

Hello Zach,

Thank you very much for your help. But the problem is still there. This is what I have done exactly. Could you please take a quick look to see is my CNTPCT_EL0 initialization enough? I observe the value in DS-5 debugger.

On one terminal:

/usr/local/DS-5_v5.29.1/bin/FVP_Base_Cortex-A35x1 -a /usr/local/DS-5_v5.29.1/examples/Bare-metal_examples_Armv8/startup_Cortex-A35x1_AC6/startup_Cortex-A35x1_AC6.axf -C bp.secure_memory=false --quantum 10 -S
terminal_0: Listening for serial connection on port 5000
terminal_1: Listening for serial connection on port 5001
terminal_2: Listening for serial connection on port 5002
terminal_3: Listening for serial connection on port 5003

Info: FVP_Base_Cortex_A35x1: CADI Debug Server started for ARM Models...

On the other terminal:

$ /usr/local/DS-5_v5.29.1/bin/debugger --cdb-entry "ARM FVP::Base_A35x1::Bare Metal Debug::Bare Metal Debug::Debug Cortex-A35" --image "/usr/local/DS-5_v5.29.1/examples/Bare-metal_examples_Armv8/startup_Cortex-A35x1_AC6/startup_Cortex-A35x1_AC6.axf"
Connected to stopped target ARM_Cortex-A35
>set $CNTP_CTL_EL0=1
>set $CNTFRQ_EL0=35000000
>p/x $CNTP_CTL_EL0
$1 = 0x5
>p/x $CNTFRQ_EL0
$2 = 0x2160EC0
>where
#0 [start64]
>p/x $CNTPCT_EL0
$3 = 0x0
>n 20
Execution stopped in EL3h mode at EL3:0x0000000080000050
In startup.S
EL3:0x0000000080000050 103,0 msr HCR_EL2, x2
>p/x $CNTPCT_EL0
$4 = 0x0
>n 20
Execution stopped in EL3h mode at EL3:0x00000000800000A0
EL3:0x00000000800000A0 196,0 isb
>p/x $CNTPCT_EL0
$5 = 0x0
>n 20
Execution stopped in EL1h mode at EL1N:0x00000000800000F0
EL1N:0x00000000800000F0 LDR x0,[pc,#360] ; [0x80000258] = 0x80007240
>p/x $CNTPCT_EL0
$6 = 0x0
>n 20
Execution stopped in EL1h mode at EL1N:0x0000000080000118
EL1N:0x0000000080000118 MSR MAIR_EL1,x1
>p/x $CNTPCT_EL0
$7 = 0x0
>n 20
Execution stopped in EL1h mode at EL1N:0x0000000080000140
EL1N:0x0000000080000140 LDR x22,[pc,#312] ; [0x80000278] = 0x800AA000
>p/x $CNTPCT_EL0
$8 = 0x0
>n 20
Execution stopped in EL1h mode at EL1N:0x0000000080000168
EL1N:0x0000000080000168 SUB x3,x5,#1
>p/x $CNTPCT_EL0
$9 = 0x0
>n 20
Execution stopped in EL1h mode at EL1N:0x0000000080000190
EL1N:0x0000000080000190 ADD x1,x1,#0x200,LSL #12
>p/x $CNTPCT_EL0
$10 = 0x0
>n 20
Execution stopped in EL1h mode at EL1N:0x00000000800001B8
EL1N:0x00000000800001B8 BL {pc}+0x178 ; 0x80000330
>p/x $CNTPCT_EL0
$11 = 0x0
>n 20
Execution stopped in EL1h mode at EL1N:0x00000000800001E0
EL1N:0x00000000800001E0 AND x4,x4,#0xffffffffffe00000
>p/x $CNTPCT_EL0
$12 = 0x0

Cortex-A35 Counter-timer Physical Count register (CNTPCT_EL0) always reads zero

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