2nd noob multiprocessor FVP question, coherency

   I have an 8 processor FVP. I can run independent code by branching on the value of MPIDR. When I do stores to the same 64 byte word, from different processors, the results are not coherent.

cpuN does a STRB to (address + N) of value 0x11. I then do a LDR of address (8 bytes) to see the result. On each processor, I see the STRB wrote the single byte in the word. If the L2 caches were coherent, whoever wrote after the first write would fetch the current Modified value from the first write, and I would see both bytes in the result. I do not.

   All the parameters I can think of in the list, and mentioned in the documentation, say I should be coherent. Any idea why it is not working?

More questions in this forum