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<?xml-stylesheet type="text/xsl" href="https://community.arm.com/utility/feedstylesheets/rss.xsl" media="screen"?><rss version="2.0" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:slash="http://purl.org/rss/1.0/modules/slash/" xmlns:wfw="http://wellformedweb.org/CommentAPI/"><channel><title>Morello Forum - Recent Threads</title><link>https://community.arm.com/developer/research/morello/f/forum</link><description>Morello is a research program led by Arm which could radically change the way we design and program processors in future, to enable better built-in security.</description><dc:language>en-US</dc:language><generator>Telligent Community 10</generator><item><title>What is in the December 2020 Maintenance Release of Morello Platform (FVP) model?</title><link>https://community.arm.com/thread/48341?ContentTypeID=0</link><pubDate>Mon, 21 Dec 2020 21:08:11 GMT</pubDate><guid isPermaLink="false">dd9e70c8-6d3c-4c71-b136-2456382a7b5c:fa7e78b9-9f4f-4b14-9b49-c4860d745d82</guid><dc:creator>Mark Inskip</dc:creator><slash:comments>0</slash:comments><comments>https://community.arm.com/thread/48341?ContentTypeID=0</comments><wfw:commentRss>https://community.arm.com/developer/research/morello/f/forum/48341/what-is-in-the-december-2020-maintenance-release-of-morello-platform-fvp-model/rss?ContentTypeId=0</wfw:commentRss><description>&lt;p&gt;Arm made a maintenance release of the Morello Platform Model (FVP) on 18 December 2020&amp;nbsp;&lt;/p&gt;
&lt;p&gt;Here are details of the updates and changes;&lt;/p&gt;
&lt;p&gt;&lt;strong&gt;1 - Package:&lt;/strong&gt;&lt;/p&gt;
&lt;ul&gt;
&lt;li&gt;Included the RuntimeLibraries to allow running the FVP on older host Linux distributions.&lt;/li&gt;
&lt;/ul&gt;
&lt;p&gt;&lt;strong&gt;2 - Morello Soc/FVP:&lt;/strong&gt;&lt;/p&gt;
&lt;ul&gt;
&lt;li&gt;VirtioP9 component has been integrated and it is working. It allows sharing a folder between the guest and host OSs.&lt;/li&gt;
&lt;li&gt;PCISBSA has been updated and demonstrated to be fully working.&lt;/li&gt;
&lt;li&gt;SoC GPIO memory map range has been aligned according to specs.&lt;/li&gt;
&lt;/ul&gt;
&lt;p&gt;&lt;strong&gt;3 - Documentation:&lt;/strong&gt;&lt;/p&gt;
&lt;ul&gt;
&lt;li&gt;FVP reference guide has been updated to instruct users on how to use the Virtio P9 and the RuntimeLibraries.&lt;/li&gt;
&lt;/ul&gt;
&lt;p&gt;&lt;strong&gt;4- Rainier CPU changes and improvements:&lt;/strong&gt;&lt;/p&gt;
&lt;ul&gt;
&lt;li&gt;Implemented changes in Morello Specification REL-01 (5): C1248, R1086, D1327&lt;/li&gt;
&lt;li&gt;Adjusted exception priorities related to MMU faults of loads/stores of valid capabilities, as well as faults related to LDCT/STCT to unsupported memory types or when the MMU is disabled to match Rainier&lt;/li&gt;
&lt;li&gt;Fixed capability fault priorities on STP, STXP capability instructions and their variants&lt;/li&gt;
&lt;li&gt;Fixed SWP capability instructions incorrectly clearing the exclusive monitor under certain conditions&lt;/li&gt;
&lt;li&gt;Fixed SPE sampling for: STCT/LDCT instructions (missing SPE PA packet,&amp;nbsp; incorrect Operation Type packet header), CSEL instructions (incorrect Operation Type packet payload)&lt;/li&gt;
&lt;li&gt;Fixed value of ESR_EL2.ISV and related fields for various Morello load/store instructions on relevant stage 2 aborts&lt;/li&gt;
&lt;li&gt;Fixed priority of System permission trap for CNTPCT_EL0, CNTVCT_EL0&lt;/li&gt;
&lt;li&gt;Improvements to implementation-defined system registers&lt;ul&gt;
&lt;li&gt;Implemented Rainier chicken switches (CPUACTLR_EL1[20:22],&amp;nbsp; CPUACTLR3_EL1[38])&lt;/li&gt;
&lt;li&gt;Exposed implementation-defined system registers via CADI&lt;/li&gt;
&lt;li&gt;Removed some implementation-defined system registers that are not&amp;nbsp;&amp;nbsp; actually present in Rainier&lt;/li&gt;
&lt;li&gt;Fixed PCC.System permission checks and/or priority of System permission trap for several implementation-defined system registers&amp;nbsp;&lt;/li&gt;
&lt;/ul&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;p&gt;The updated Morello FVP available to download from &lt;a href="https://developer.arm.com/tools-and-software/open-source-software/arm-platforms-software/arm-ecosystem-fvps"&gt;https://developer.arm.com/tools-and-software/open-source-software/arm-platforms-software/arm-ecosystem-fvps&lt;/a&gt;&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>How to enable a shared directory between the booted guest OS on Morello FVP and the host linux machine</title><link>https://community.arm.com/thread/48131?ContentTypeID=0</link><pubDate>Thu, 26 Nov 2020 17:08:49 GMT</pubDate><guid isPermaLink="false">dd9e70c8-6d3c-4c71-b136-2456382a7b5c:2fbe8f33-8611-41ba-a9b2-4a783a7d1cc1</guid><dc:creator>Andy Nisbet</dc:creator><slash:comments>5</slash:comments><comments>https://community.arm.com/thread/48131?ContentTypeID=0</comments><wfw:commentRss>https://community.arm.com/developer/research/morello/f/forum/48131/how-to-enable-a-shared-directory-between-the-booted-guest-os-on-morello-fvp-and-the-host-linux-machine/rss?ContentTypeId=0</wfw:commentRss><description>&lt;p&gt;Hi,&lt;/p&gt;
&lt;p&gt;I want to experiment with capability enabled LLVM - but would like to have a shared directory&amp;nbsp; between the Morello FVP&amp;nbsp; and the host linux. Please could you give some more detailed instructions on this, sorry if I have missed anything obvious in the documentation.&amp;nbsp;&lt;/p&gt;
&lt;p&gt;Thanks,&lt;/p&gt;
&lt;p&gt;Andy&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>Morello: Frequently Asked Questions (FAQs)</title><link>https://community.arm.com/thread/47894?ContentTypeID=0</link><pubDate>Fri, 23 Oct 2020 14:59:51 GMT</pubDate><guid isPermaLink="false">dd9e70c8-6d3c-4c71-b136-2456382a7b5c:630083d7-e939-4b17-955c-a19e196a7af6</guid><dc:creator>Ash Wilding</dc:creator><slash:comments>1</slash:comments><comments>https://community.arm.com/thread/47894?ContentTypeID=0</comments><wfw:commentRss>https://community.arm.com/developer/research/morello/f/forum/47894/morello-frequently-asked-questions-faqs/rss?ContentTypeId=0</wfw:commentRss><description>&lt;p&gt;&lt;strong&gt;Contents&lt;/strong&gt;&lt;/p&gt;
&lt;ul&gt;
&lt;li&gt;&lt;a href="#model"&gt;What is the Morello Platform Model?&lt;/a&gt;&lt;/li&gt;
&lt;li&gt;&lt;a href="#examples"&gt;What examples are available?&lt;/a&gt;&lt;/li&gt;
&lt;li&gt;&lt;a href="#compile"&gt;How can I compile code for Morello?&lt;/a&gt;&lt;/li&gt;
&lt;li&gt;&lt;a href="#software"&gt;Where can I download the firmware and software stack for the Morello Platform Model?&lt;/a&gt;&lt;/li&gt;
&lt;li&gt;&lt;a href="#limitations"&gt;What can I do with the Morello reference software stack?&lt;/a&gt;&lt;/li&gt;
&lt;li&gt;&lt;a href="#support"&gt;Where can I get support?&lt;/a&gt;&lt;/li&gt;
&lt;li&gt;&lt;a href="#trustzone"&gt;How does the CHERI security architecture relate to Arm&amp;#39;s existing TrustZone solutions?&lt;/a&gt;&lt;/li&gt;
&lt;li&gt;&lt;a href="#pay"&gt;Do I need to pay for, or request access to, the Morello Platform Model?&lt;/a&gt;&lt;/li&gt;
&lt;li&gt;&lt;a href="#board"&gt;How and when can I get a Morello development board?&lt;/a&gt;&lt;/li&gt;
&lt;li&gt;&lt;a href="#arch"&gt;Which Arm architectural states support Morello?&lt;/a&gt;&lt;/li&gt;
&lt;li&gt;&lt;a href="#isa"&gt;Which Arm ISA does Morello use?&lt;/a&gt;&lt;/li&gt;
&lt;/ul&gt;
&lt;p&gt;&lt;strong&gt;&amp;nbsp;&lt;/strong&gt;&lt;/p&gt;
&lt;p&gt;&lt;strong&gt;&lt;a id="model"&gt;&lt;/a&gt;What is the Morello Platform Model?&lt;/strong&gt;&lt;/p&gt;
&lt;p&gt;The Morello Platform Model is an open access Fixed Virtual Platform (FVP) development platform, aligned with the future development board, and is available to download from &lt;a href="https://developer.arm.com/tools-and-software/open-source-software/arm-platforms-software/arm-ecosystem-fvps"&gt; Arm&amp;#39;s Ecosystem FVP Developer page&lt;/a&gt;.&lt;/p&gt;
&lt;p&gt;FVPs use Arm technology to create a virtual model of the system hardware that can be run as an executable in a development environment. They use binary translation technology to deliver functional simulations of Arm-based systems, including processor, memory, and peripherals. They implement a programmer&amp;#39;s view suitable for software development and enable execution of full software stacks, providing a widely available platform ahead of silicon.&lt;/p&gt;
&lt;p&gt;&lt;a href="https://developer.arm.com/documentation/102225/latest"&gt; See here to get started using the Morello Platform Model&lt;/a&gt;.&lt;/p&gt;
&lt;p&gt;&lt;strong&gt;&amp;nbsp;&lt;/strong&gt;&lt;/p&gt;
&lt;p&gt;&lt;strong&gt;&lt;a id="examples"&gt;&lt;/a&gt;What examples are available?&lt;/strong&gt;&lt;/p&gt;
&lt;p&gt;Arm Development Studio Morello Edition ships with an example project that can be run on the Morello Platform Model.&lt;/p&gt;
&lt;p&gt;&lt;a href="https://developer.arm.com/documentation/102233/latest"&gt; See here to get started using Arm Development Studio Morello Edition&lt;/a&gt;.&lt;/p&gt;
&lt;p&gt;&lt;strong&gt;&amp;nbsp;&lt;/strong&gt;&lt;/p&gt;
&lt;p&gt;&lt;strong&gt;&lt;a id="compile"&gt;&lt;/a&gt;How can I compile code for Morello?&lt;/strong&gt;&lt;/p&gt;
&lt;p&gt;Morello is supported by the following open source LLVM-based toolchains based on the CHERI Clang/LLVM toolchain from the University of Cambridge. Please note that these are experimental toolchains and as such some features may not yet be available or fully functional.&lt;/p&gt;
&lt;ul&gt;
&lt;li&gt;Android CHERI LLVM/Clang toolchain, which includes a C/C++ compiler (clang), linker (lld), debugger (lldb), various utilities (such as assembler &amp;amp; disassembler), and run-time libraries.&lt;/li&gt;
&lt;li&gt;Bare-metal toolchain for architecture exploration projects, which includes a C/C++ compiler (clang), linker (lld), a standard C library (newlib), a standard C++ library (libc++, libc++abi) and various utilities (such as assembler &amp;amp; disassembler).
&lt;ul&gt;
&lt;li&gt;&lt;a href="https://developer.arm.com/architectures/cpu-architecture/a-profile/morello/morello-resources/development-tools#arm-development-studio"&gt; Arm Development Studio Morello Edition&lt;/a&gt; is also available as a development environment for the bare-metal configuration.&lt;/li&gt;
&lt;/ul&gt;
&lt;/li&gt;
&lt;li&gt;AArch64 Linux CHERI LLVM/Clang toolchain, which is an experimental AArch64 hosted variant primarily intended to be used together with &lt;a href="https://developer.arm.com/architectures/cpu-architecture/a-profile/morello/development-tools#instruction-emulator"&gt; Arm&amp;#39;s Morello Instruction Emulator&lt;/a&gt;. It includes a C/C++ compiler (clang), linker (lld), various utilities and run-time libraries, but does not include a C library.
&lt;ul&gt;
&lt;li&gt;&lt;a href="https://developer.arm.com/documentation/ka002048/1-0/?lang=en"&gt; See this knowledge base article for more information&lt;/a&gt;.&lt;/li&gt;
&lt;/ul&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;p&gt;The following compiler flags should be used to enable Morello code generation:&lt;/p&gt;
&lt;pre&gt;-march=morello+c64 -mabi=purecap&lt;/pre&gt;
&lt;p&gt;For more information, see the &lt;a href="https://git.morello-project.org/morello/llvm-project-releases/-/blob/morello/release-docs-1.0/UserGuide.pdf"&gt;LLVM compiler with Morello support user guide here&lt;/a&gt;.&lt;/p&gt;
&lt;p&gt;&lt;strong&gt;&amp;nbsp;&lt;/strong&gt;&lt;/p&gt;
&lt;p&gt;&lt;strong&gt;&lt;a id="software"&gt;&lt;/a&gt;Where can I download the firmware and software stack for the Morello Platform Model?&lt;/strong&gt;&lt;/p&gt;
&lt;p&gt;A reference open source software stack is available comprising:&lt;/p&gt;
&lt;table&gt;
&lt;thead&gt;
&lt;tr&gt;
&lt;th&gt;Component&lt;/th&gt;
&lt;th&gt;Name&lt;/th&gt;
&lt;/tr&gt;
&lt;/thead&gt;
&lt;tbody&gt;
&lt;tr&gt;
&lt;td&gt;System Control Processor firmware&lt;/td&gt;
&lt;td&gt;&lt;a href="https://github.com/ARM-software/SCP-firmware" rel="noopener noreferrer" target="_blank"&gt;SCP-firmware&lt;/a&gt;&lt;/td&gt;
&lt;/tr&gt;
&lt;tr&gt;
&lt;td&gt;CPU Secure world firmware&lt;/td&gt;
&lt;td&gt;&lt;a href="https://www.trustedfirmware.org/" rel="noopener noreferrer" target="_blank"&gt;Trusted Firmware-A&lt;/a&gt;&lt;/td&gt;
&lt;/tr&gt;
&lt;tr&gt;
&lt;td&gt;CPU Normal world firmware&lt;/td&gt;
&lt;td&gt;&lt;a href="https://github.com/tianocore/edk2" rel="noopener noreferrer" target="_blank"&gt;EDK II UEFI&lt;/a&gt;&lt;/td&gt;
&lt;/tr&gt;
&lt;tr&gt;
&lt;td&gt;Boot loader&lt;/td&gt;
&lt;td&gt;&lt;a href="https://www.gnu.org/software/grub/" rel="noopener noreferrer" target="_blank"&gt;GRUB&lt;/a&gt;&lt;/td&gt;
&lt;/tr&gt;
&lt;tr&gt;
&lt;td&gt;OS kernel&lt;/td&gt;
&lt;td&gt;&lt;a href="https://source.android.com/devices/architecture/kernel/android-common" rel="noopener noreferrer" target="_blank"&gt;Android Common Kernel (Linux)&lt;/a&gt;&lt;/td&gt;
&lt;/tr&gt;
&lt;tr&gt;
&lt;td&gt;OS user-space&lt;/td&gt;
&lt;td&gt;&lt;a href="https://www.android.com/" rel="noopener noreferrer" target="_blank"&gt;Android&lt;/a&gt;&lt;/td&gt;
&lt;/tr&gt;
&lt;/tbody&gt;
&lt;/table&gt;
&lt;p&gt;&lt;a href="https://www.morello-project.org/"&gt; See here to get started downloading, building, and running this reference open source software stack on the Morello Platform Model&lt;/a&gt;.&lt;/p&gt;
&lt;p&gt;&lt;strong&gt;&amp;nbsp;&lt;/strong&gt;&lt;/p&gt;
&lt;p&gt;&lt;strong&gt;&lt;a id="limitations"&gt;&lt;/a&gt;What can I do with the Morello reference software stack?&lt;/strong&gt;&lt;/p&gt;
&lt;p&gt;Please be aware that Morello is still in the early stages of development, and as such there are limitations on the kind of applications that can be developed.&lt;/p&gt;
&lt;p&gt;For full details of the current limitations, please &lt;a href="https://www.morello-project.org/"&gt; refer to the README files in the Morello reference software stack git repository&lt;/a&gt;.&lt;/p&gt;
&lt;p&gt;&lt;strong&gt;&amp;nbsp;&lt;/strong&gt;&lt;/p&gt;
&lt;p&gt;&lt;strong&gt;&lt;a id="support"&gt;&lt;/a&gt;Where can I get support?&lt;/strong&gt;&lt;/p&gt;
&lt;p&gt;You are welcome to ask questions and start discussions here on our &lt;a href="/developer/research/morello/"&gt; Morello Community Forums&lt;/a&gt;.&lt;/p&gt;
&lt;p&gt;&lt;strong&gt;&amp;nbsp;&lt;/strong&gt;&lt;/p&gt;
&lt;p&gt;&lt;strong&gt;&lt;a id="trustzone"&gt;&lt;/a&gt;How does the CHERI security architecture relate to Arm&amp;#39;s existing TrustZone solutions?&lt;/strong&gt;&lt;/p&gt;
&lt;p&gt;Morello is not directly related to TrustZone; capabilities can be applied to Secure world or Normal world software stacks. For more information please see &lt;a href="https://www.cl.cam.ac.uk/techreports/UCAM-CL-TR-941.pdf"&gt; CUCLs intro to CHERI&lt;/a&gt;.&lt;/p&gt;
&lt;p&gt;&lt;strong&gt;&amp;nbsp;&lt;/strong&gt;&lt;/p&gt;
&lt;p&gt;&lt;strong&gt;&lt;a id="pay"&gt;&lt;/a&gt;Do I need to pay for, or request access to, the Morello Platform Model?&lt;/strong&gt;&lt;/p&gt;
&lt;p&gt;No, the Morello Platform Model is free of charge and available to download from &lt;a href="https://developer.arm.com/tools-and-software/open-source-software/arm-platforms-software/arm-ecosystem-fvps"&gt; Arm&amp;#39;s Ecosystem FVP Developer page&lt;/a&gt;.&lt;/p&gt;
&lt;p&gt;&lt;strong&gt;&amp;nbsp;&lt;/strong&gt;&lt;/p&gt;
&lt;p&gt;&lt;strong&gt;&lt;a id="board"&gt;&lt;/a&gt;How and when can I get a Morello development board?&lt;/strong&gt;&lt;/p&gt;
&lt;p&gt;Morello development boards will only be available to a select list of industry partners and universities, as decided by the UK Research and Innovation (UKRI). They will not be available for general sale or supplied directly by Arm.&lt;/p&gt;
&lt;p&gt;&lt;strong&gt;&amp;nbsp;&lt;/strong&gt;&lt;/p&gt;
&lt;p&gt;&lt;strong&gt;&lt;a id="arch"&gt;&lt;/a&gt;Which Arm architectural states support Morello?&lt;/strong&gt;&lt;/p&gt;
&lt;p&gt;Morello extends the Armv8.2-A Architecture, and is only available in AArch64 state (no support for AArch32). Further, Morello mandates only little-endian data accesses.&lt;/p&gt;
&lt;p&gt;&lt;strong&gt;&amp;nbsp;&lt;/strong&gt;&lt;/p&gt;
&lt;p&gt;&lt;strong&gt;&lt;a id="isa"&gt;&lt;/a&gt;Which Arm ISA does Morello use?&lt;/strong&gt;&lt;/p&gt;
&lt;p&gt;Morello extends the A64 ISA, adding instructions to manipulate and use capabilities to a limited extent. Morello also introduces a variant of the A64 ISA, C64, providing a richer set of instructions to manipulate and use capabilities.&lt;/p&gt;
&lt;p&gt;&lt;strong&gt;&amp;nbsp;&lt;/strong&gt;&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item></channel></rss>