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What is in the May 2021 Maintenance Release of Morello Platform (FVP) model?

Mark Inskip

Arm made a maintenance release of the Morello Platform Model (FVP) on 27 May 2021. What is in this release?

Parents
  • +1
    The Morello FVP release 1.3 includes SoC and CPU alignments with the RTL, hence provides fixes to all reported bugs on the CPU backlog.

    Here are details of the updates and changes;

    1 - SoC level alignment:
    •  Aligned generic timer peripheral with the RTL
    2- CPU Rainier model changes and improvements:
    • Aligned CPU behavior with the RTL
    • Updated stage1 SC bit and takes fault on S2
    • Prioritize S1 permission fault over S2 on stage 1 walk
    • Fixed access to DISR_EL1 from EL0 and trap if PCC.S is 0
    • Fixed SC update fault when S1 sdbm is false
    • Fixed return address of a block in which watchpoint is present
    • Fixed incorrect watchpoint address
    • Fixed copying SPSR.C64 to PSTATE.C64 on ERET EL3
    • Fixed mismatch on MRS to MVFRx_EL1
    • Fixed traps at different exception levels
    • Fixed incorrect SPSR_ELx.C64 state on an ERET
    • Fixed WnR bit disagreement on SC faults
    • Reduced STX(L) watchpoint size from 128 to 64 byte
    • Fixed base address register to align PC load
    • Fixed LDPBLR: update link register and then data
Reply
  • +1
    The Morello FVP release 1.3 includes SoC and CPU alignments with the RTL, hence provides fixes to all reported bugs on the CPU backlog.

    Here are details of the updates and changes;

    1 - SoC level alignment:
    •  Aligned generic timer peripheral with the RTL
    2- CPU Rainier model changes and improvements:
    • Aligned CPU behavior with the RTL
    • Updated stage1 SC bit and takes fault on S2
    • Prioritize S1 permission fault over S2 on stage 1 walk
    • Fixed access to DISR_EL1 from EL0 and trap if PCC.S is 0
    • Fixed SC update fault when S1 sdbm is false
    • Fixed return address of a block in which watchpoint is present
    • Fixed incorrect watchpoint address
    • Fixed copying SPSR.C64 to PSTATE.C64 on ERET EL3
    • Fixed mismatch on MRS to MVFRx_EL1
    • Fixed traps at different exception levels
    • Fixed incorrect SPSR_ELx.C64 state on an ERET
    • Fixed WnR bit disagreement on SC faults
    • Reduced STX(L) watchpoint size from 128 to 64 byte
    • Fixed base address register to align PC load
    • Fixed LDPBLR: update link register and then data
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