Smaller, cheaper, more efficient. These are the three big considerations when designing a power converter, and usually one design prioritizes just one theme, while keeping the other two within acceptable limits. Designing a power converter for M0N0, Arm Research's ultra-low power microcontroller, is no different. With only three tiny off-the shelf passive components and merely 0.4mm2 of silicon area, cost is well-controlled. The solution size is suitable for many applications. The reference design employs a 1.6mm x 0.8mm ceramic inductor and two 1.5mm x 0.8mm ceramic capacitors, and still further size reduction could be investigated. Efficiency is where the devil is hiding. Out of the headline-grabbing specification points mentioned here or there, one may notice the striking results: 10µW active power, single battery cell operation (1V – 1.5V) and 20µW/MHz for an Arm Cortex-M33™ with DSP and SIMD extensions. At first sight, there is very little that relates to the power-efficiency of a power converter. Why write a blog post on such a trivial topic? Well, the proof of the pudding is in the eating, is it not? Let us dive into the arcane technology under the well-polished hood.
The M0N0 context presented in figure 1 appears relatively simple. The battery that supplies the entire system presents a voltage ranging between 1V and 1.5V, depending on its state of charge. On the other hand, the CPU is optimized for low-power operation in the sub-threshold region of the transistors. It requires a supply voltage ranging between 0.4V and 0.75V, depending on the clock frequency the programmer wants to use. A power converter is needed to convert the battery voltage into the CPU supply voltage.
Figure 1: A M0N0-based system
This is a standard voltage step-down case, and many options, are available to the designer. A simple linear regulation, Low Dropout (LDO), as presented in figure 2, could perform admirably with a comfortable worst-case drop of 250mV, a maximum output power in the mW range and a maximum theoretical efficiency of less than 33% in typical conditions at minimum CPU performance. However, projected efficiency of an actual LDO under the M0N0 constraints would be closer to 25%. With such a solution, M0N0 would be advertised as 25uW or 30uW active power. Still not bad, but Arm researchers cannot stand losing 75% of the energy of a battery in a single transistor!
Figure 2: Simplified schematic of a LDO for M0N0
Enter switched-mode power supplies. The highly efficient structure of a buck converter presented in figure 3 seems best suited for M0N0, where efficiency is primary and other parameters are secondary to this. Just two transistors, one inductor and one capacitor. It should be easy to reach unprecedented levels of energy efficiency in a very short time, should it not?
Figure 3: Simplified schematic of a Buck converter for M0N0
It is and it is not. M0N0 is also a leakage-constrained design, and we wanted to keep its physical size within acceptable limits. To cut a long story short, assuming the transistors of the buck power-stage are correctly controlled, the efficiency of this structure lies around 85% over the range of operation. Let us simply add a pulse frequency modulator, which will control the two power transistors to reach sky-high efficiency levels. However, control is the elephant in the room, and its effect on the power efficiency of the converter cannot be neglected at those power levels. Figure 4 presents a simplified view of the power converter in its environments with power flow annotated.
Figure 4: Simplified power flow diagram for M0N0
The digital subsystem requires a power Pload to operate at the chosen operating point, the power-stage of the buck converter delivers that power while dissipating the power Plossps, and the control of the converter also takes the power Plossctrl to operate. Pperiph is the power dissipated by other circuits in the battery voltage domain. This power dissipation is unavoidable but almost negligible for M0N0. We are interested in delivering the right Pload power while keeping Plossps and Plossctrl as small as possible. In other words, maximizing the overall efficiency and getting as much benefit as possible from the subthreshold operation of the CPU subsystem. The M0N0 headline advertises 10 µW active power. That power is the power-drawn from the battery, Pbat, and includes the power-converter dissipations, Plossps and Plossctrl, as well as Pperiph.
Figure 5: Buck efficiency for an 85% efficient power-stage and different power dissipations of the control circuit
Figure 5 illustrates the impact of the control power dissipation on the buck efficiency. On the X-axis is the Cortex subsystem operating power. On the Y-axis is the system power-transfer efficiency that goes slightly beyond the Buck-converter efficiency and is defined as:
The power-stage of the buck converter operating in Pulse Frequency Modulation is modelled as an 85% flat efficiency, a model that is accurate enough at this level of detail. Two models are presented for the control and peripheral power dissipation, Plossctrl + Pperiph. A state-of-the-art type scenario at 30µW discards the 10µW operation target from the start. If the Cortex subsystem requires 6µW, and the power-stage of the buck converter is 85% efficient, 10µW operation can be achieved with 2.4µW control and peripheral power. This is what M0N0 needs, and is ten times more power efficient than state-of-the-art solutions. This translates into designing a buck converter with about 65% efficiency, a 6µW output power rather than sub-20% at the same output power. That emphasizes how every µW counts when designing a complete microcontroller system. One of the key questions when designing a power converter for M0N0 is how to control a buck converter with less than 2.4µW, including all references?
There is a lot more that could be written on this topic. To minimize voltage margins, and the effect of process variations we put in place what we call ‘performance regulation’ instead of relying on voltage regulation. We used a heavily mixed-signal approach to reduce to the bare minimum any continuous bias current within the control circuit of the buck converter. Furthermore, all designs have been power-optimized without sacrificing the essential performances.
You can find a partial description of those topics in our latest article published in the IEEE Journal of Solid-State Circuits: “A Supply Voltage Control Method for Performance Guaranteed Ultra-Low-Power Microcontroller”. This article describes the circuit used to sense the converter output, cornerstone of our performance regulation concept that frees our design from the large process and temperature variation effects on subthreshold designs. It also enables a power conversion efficiency above 50% at 2.5µW output power, thanks to its low power consumption, but still performs well when high power output is required. Did we mention how quickly M0N0 responds to a wake-up request? Low power is not necessarily slow, and that is also thanks to our innovative control circuit.
Read the Full Paper Contact Benoit Labbe
What else is there to know about M0N0? Explore our research so far using the following links.M0N0: An Arm Research platform for N-ZERO sensors
M0N0: A tale of three devices