• Architectural tricks to maximize memory bandwidth

    Unexplained Read/Write latency can be attributed to cache hit-ratio, burst length, commands-in-a-row, AXI Bus arbitration, and video pipeline. During this Webinar, we will present the system-level modeling of complex video pipelines and their interface…

    • https://www.youtube.com/embed/c0EgjJHESME
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  • Selecting the right hardware configuration for a Video Processing SoC

    Battery life is the most important requirement for 4K systems.  In this video, we cover the trade-off between Power and Performance when making implementation decisions. We should the components required, the levels of abstraction and the accuracy of…

    • https://www.youtube.com/embed/6wAH1ImRGUw
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  • Exploring the ARM CoreLink™ CCI-500 performance envelope – Part 2

    Introduction

    In Part 1 of this blog series (found here ) we introduced the ARM CoreLinkTM CCI-500 Cache Coherent Interconnect and described some of the new configurable features which are available over and above what was available with the previous generation…

  • How to Measure and Optimize the System Performance of a Smartphone RTL Design - Part 3

    By William Orme, Strategic Marketing Manager, Arm and Nick Heaton, Distinguished Engineer, Cadence

    This is Part 3 of a 4 part series. Links below

    Part 3

    Use-case Performance Analysis

    In the previous two parts we introduced the challenges facing designers…

  • How to Measure and Optimize the System Performance of a Smartphone RTL Design - Part 2

    By William Orme, Strategic Marketing Manager, Arm and Nick Heaton, Distinguished Engineer, Cadence

    This is Part 2 of a 4 part series. Links below

    Part 2

    Performance Characterization

    Because of the complexity of assembling and configuring the multitude…