• ARMv8 Exception level on Startup

    Hi,

    When i power on a ARM cortex A57, How many of the 4 Exception levels will be supported?

    How can i set such that only exception levels EL0 and EL1 are supported in my program? How can i activate each exception levels?

    I have to set it such that normally…

  • Embedded ARMv8 dev board

    I'm an arduino guy looking for more power and I'd like to start using the high performance ARM chips such as the A57 and soon the A75, but I'm having an impossible time finding dev boards for anything other than some older ARM chips (I think the highest…

  • Booting sama5d2 with lpddr2

    I'm having a SAMA5D26C with a LPDDR2 EDB1332BDBH-1. The CPU boots successfully ROMBOOT and is able to load at91bootstrap from QSPI memory. I get debug output from at91bootstrap, but I fail to load linux.

    Investigating this further show me that the…

  • Interrupt status in Aarch64

    Hello, 

    In Cortex, A9 CPU register CPSR tells the current execution mode , bit M[3;0]

    I am looking for if there is similar register present in A64 architecture . 

    Reading ESR_EL3/EL2/EL1, I think this is difficult to determine, if system in IRQ mode or…

  • How to read ARM A9 registers in C?

    Hello!

    I'm using a Zybo board with a dual-core ARM Cortex-A9 processor and I'm trying to read (and then write) the registers of the processor. How can I read these values into variables in C code?

     

    Thank you!

  • ARM Zynq Cortex-A53: implementing complex matrix inversion

    Hello,

    I am developing embedded software on Zynq MPSOC Cortex-A53 (Armv7/Armv8) for image processing, and I need some help for developing a specific algorithm.

    The algorithm involves many calculations of FFT and matrix using. As highest priority, we…

  • Looking for ARM A15 simulator or compiler details on TI Chip

    Hello , 

    We are working on TI chip which holds A15 as one of the main core in the HW . We are looking for some technical support on A15 . 

    I appreciate someone from technical team could reach and help me out on that at the earliest . 

    I will share further…

  • ARMV7A virtualization

    Hi,

    I am working on a hardware platform having 2 Cortex-A15 cores (with virtualization extensions). For routing IRQ's at PL2 to PL3 ( to hypervisor mode), I am setting HCR.IMO bit and it is working fine for core-0. If I set the HCR.IMO for core-1, will…

  • After Embedded World: What’s Next for Embedded ML?

    There’s no denying that Embedded World (EW) is a whirlwind – 1000 exhibits, 35,000 visitors and over 2,000 industry participants – but now that it’s all over and the dust has settled, I wanted to take a moment to reflect on its impact, and consider the…

  • Can I place the System MMU (SMMU-400) before the DRAM Memory Controller (DMC-400)?

    Hi all,

     

    I have two A15 CPUs and 1GByte of DRAM memory. I want to dedicate 0.5GByte of memory to each CPU. Would the following system work?

     

    (A15)  (A15)

       |          |

    ----CCI----…

  • What flow should I execute to make cache and MMU work properly when I turn into non secure world?

    In A7 platform with TZ extension , I know that there is a virtual MMU for non secure world, and I think it should be enabled after entering non secure world.

    But the most confusing thing is that what has to be done with cache-----clean , invalidate or…

  • You’ve talked about A75 system guidance today, what is next?

    This question was asked in the 'How to optimize a system with the latest ARM DynamIQ processors' webinar.  You can view all other related questions in this blog post. 

  • AMP system on Cortex-A9. How to do it?

    Hello everyone. I'm trying to understand how to create and make work two separate baremetal programms on two cores of cortex-a9. I'm using Cyclone V SoC. DS-5, arm compiller 5, DE1-SoC board by terasic. I already understand how to work with main core…

  • does ARM v8 bus architecture & related IPs be compatible with v7 core?

    I would like to get some confirmation that if we replace A53/A72 with A7/A9 while the SoC architecture is still based on ARM v8 bus & IPs (e.g. CCI400, NIC400, TZC400, GIC500, BP141), does such design feasible and workable?

  • Announcing Arm Leading Edge: pushing the limits of rich embedded computing on Arm

    Today we are announcing Arm Leading Edge, a new awareness initiative to showcase the exceptional work being done by key partners to push the limits of what is possible in edge computing.

    Arm Leading Edge partners, among others, are building the next generation…

  • New online training course – Arm Cortex processor behaviors

    We are very pleased to announce a new online training topic – Arm Cortex processor behaviors.

    About the course

    This course builds on our series of topics that introduce the A, R, and M profiles of the Arm architecture and is targeted primarily at hardware…

  • Arm and Synopsys Extend Collaboration and Kick off WW Workshop Series

    Arm and Synopsys just announced an extension of the long-standing collaboration between the companies, including a multi-year subscription agreement for access to Arm IP (CPU and GPU cores, system IP, physical IP and POP) to improve power, performance…

    • https://www.synopsys.com/implementation-and-signoff/resources/events/2018-arm-synopsys-workshops.html
    • View

  • EW17 day 3 blog: The evolution of embedded computing

    (This is a wrap up of my thoughts from day 3 of Embedded World 2017. For highlights from day 1 and 2, check out EW17 day 1 blog: IoT security and Lego cities and EW17 day 2 blog: All about automotive)

    One of the things that has struck me walking around…

  • Could I use Cortex-A for embedded applications?

    I need a little digital io for my project since cortex-m is not economical for me I need to know can i use Cortex-a to do some embedded jobs?

  • SMP Linux on a Minimal Dual-Core ARM Cortex-A15 System

    Previously, I explained how to create a minimal, single-core ARM® Cortex™-A15 system running Linux®. In this article I will update the hardware design to use a dual-core ARM Cortex-A15 CPU and run SMP (Symmetric Multiprocessing) Linux. While the first…

  • Embedded Developer Feature: Jens Bauer, GPIO Design Engineer

    Get to know the Embedded Developer...

    This is a monthly series featuring embedded developers of the ARM Connected Community.


    Jens Bauer.png

    Name: jensbauer

    Company: GPIO

    Job Title: Design Engineer

    Location: Herning, Denmark

    Developer History

    Before GPIO, I've been working…

  • Freescale Adopts Cortex-M to Address Exponential Electronic Content Growth in Vehicles

    Yesterday in Shanghai, Freescale Semiconductor made a significant announcement to bring their Kinetis EA series of MCUs into the automotive market.

    Thus far, ARM’s success in automotive has mainly been with the ARM® Cortex®-A and Cortex…

  • Embedded Developer Feature: Paul Beckmann, Founder of DSP Concepts

    Get to know the Embedded Developer...

    This is a monthly series featuring embedded developers of the ARM Connected Community.

    Paul_Beckmann.jpg

    Name: pbeckmann

    Company: DSP Concepts

    Job Title: Founder/CEO

    Location: Santa Clara, CA

    Developer History

    Paul Beckmann received his BS…

  • Eight innovative ARM-based Kickstarter projects

    In the spirit of some of the more well-known ARM-based development boards and their popular communities, I was curious what other innovative ideas are out there being crowdsourced. Just a bit of research quickly revealed eight ARM-based embedded projects…

  • Introduction to the QVN Protocol

    I created a short introduction to the QVN protocol used with the QVN-400 plugin to NIC-400 and with the DMC-400 dynamic memory controller. This is a non-confidential introductory-level document for those seeking to understand how QVN works and what issues…

    • QVN-Introduction-CC.pdf