• How can I use imx6 in Asymmetric (***) mode?

    I would like to use iMX6 in asymmetric mode (Windows EC7 + Linux). Is that anyhow possible? Marco

  • Cortex A9 dual core - How to achieve an AMP system without an RTOS?

    One of my customer is considering to use Cortex A9 dual core device for a computational intensive task (For the sake of discussion, lets assume an high end

    image analysis task). Due to cost or other over head reasons, he/she does not prefer to use an RTOS…

  • TCP/IP stack for Cortex-A9 MPCore

    Hi,

    I'm currently working on a project based on the Arria V SoC FPGA (ARM Cortex-A9 MPCore). The goal of this project is to run a high speed ethernet link.

    For some reasons the customer don't want to use a Linux kernel on the ARM. His wish is to have…

  • Anyone knows of any Cortex-A9 development boards?

    We've been using TI's Panda board but it seems to give us quite a bit of trouble.  As a result we can't profile the information that we would like.  Does anyone know of any other development boards out there that has a Cortex-A9 on it?  And what experiences…

  • ARM Linux: Can I control cache flush and invalidation in user space?

    These days I'm using Xilinx SoC to design a software, which shares memory between Cortex-A cores and FPGA.

    I've tried reserve memory in Linux and mmap() /dev/mem. The problem is if I use O_SYNC, it very slow since

    my software access every byte computed…

  • L1 Cache Eviction Corrupting DDR on A9

    Hi All!

    I am working with a Xilinx Zynq 7000 SoC which uses the Cortex A9 as a CPU.

    I've observed a problem wherein a section of memory marked strongly-ordered and non-cacheable (0xc02) in the MMU table gets corrupted by what appears to be L1 evictions…

  • How to configure Interrupt vector table ?

    Hi,
    I am using I.MX6Q Sabre sd board (cortex-a9 ). I am trying to build custom image with my own start script and ld script. The image is to be loaded with u-boot. Where should i place the Interrupt vector table? Now, when i reffered the "1.1.0_iMX6_Platform_SDK…

    • 10800.zip

  • Converting virtual address of Instruction fault address register to physical address in cotex A9

    Content of IFAR=0xaa4e8ef0

    IFSR=0x0000000d

    DFSR:0x00000000

    DFAR:0x00004000

     

    How to find Physical address form this?

  • Interrupt status in Aarch64

    Hello, 

    In Cortex, A9 CPU register CPSR tells the current execution mode , bit M[3;0]

    I am looking for if there is similar register present in A64 architecture . 

    Reading ESR_EL3/EL2/EL1, I think this is difficult to determine, if system in IRQ mode or…

  • How to read ARM A9 registers in C?

    Hello!

    I'm using a Zybo board with a dual-core ARM Cortex-A9 processor and I'm trying to read (and then write) the registers of the processor. How can I read these values into variables in C code?

     

    Thank you!

  • AMP system on Cortex-A9. How to do it?

    Hello everyone. I'm trying to understand how to create and make work two separate baremetal programms on two cores of cortex-a9. I'm using Cyclone V SoC. DS-5, arm compiller 5, DE1-SoC board by terasic. I already understand how to work with main core…

  • Embedded Developer Feature: Jens Bauer, GPIO Design Engineer

    Get to know the Embedded Developer...

    This is a monthly series featuring embedded developers of the ARM Connected Community.


    Jens Bauer.png

    Name: jensbauer

    Company: GPIO

    Job Title: Design Engineer

    Location: Herning, Denmark

    Developer History

    Before GPIO, I've been working…

  • Eight innovative ARM-based Kickstarter projects

    In the spirit of some of the more well-known ARM-based development boards and their popular communities, I was curious what other innovative ideas are out there being crowdsourced. Just a bit of research quickly revealed eight ARM-based embedded projects…

  • ARMv7-A - Power to the People

    Recently, I wrote an article called “Navigating the Cortex Maze” (Navigating the Cortex Maze) That was intended as an easy way-in to the ARM processor range, covering Cortex-A (architecture ARMv7-A), Cortex-R (ARMv7-R) and Cortex-M (ARMv7…