• Exception handlers and interrupt

    Hi All,

            i went through this link

    http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dui0471g/BABGCFHB.html

    and related a53 vector table implementation.

    in this regard, i have a question

    1. Say a processor gets stuck in exception handler due…

  • GIC 3.0's SGI interrupt latency seems much bigger than GIC 2.0

    Hi,

    I tested SGI interrupt latency, it seems that GIC3.0's SGI interrupt latency are much bigger than GIC2.0.

    How to test:

    GIC3.0:

    1. read timestamp(t01)

    2. core0 write  ICC_SGI0R_EL1 to trigger core1, read timestamp(t02)

    3. isr in core1, read timestamp…

  • What kind of memory barrier should be followed by writes ICC_SGI1R_EL1?

    As we all know, ICC_SGI1R_EL1 is used to produce another core's interrupt.

    I am a software engineer.

    My question is what kind of memory barrier should be followed by writes ICC_SGI1R_EL1?

    This question related to the implementation of the instruction…