• GIC 3.0's SGI interrupt latency seems much bigger than GIC 2.0

    Hi,

    I tested SGI interrupt latency, it seems that GIC3.0's SGI interrupt latency are much bigger than GIC2.0.

    How to test:

    GIC3.0:

    1. read timestamp(t01)

    2. core0 write  ICC_SGI0R_EL1 to trigger core1, read timestamp(t02)

    3. isr in core1, read timestamp…

  • What kind of memory barrier should be followed by writes ICC_SGI1R_EL1?

    As we all know, ICC_SGI1R_EL1 is used to produce another core's interrupt.

    I am a software engineer.

    My question is what kind of memory barrier should be followed by writes ICC_SGI1R_EL1?

    This question related to the implementation of the instruction…

  • GIC 500 :: Not able to find the definition for GICD_IROUTERn register

    Can someone please point me to the documentation where I can find the definition for GICD_IROUTERn register. I see it mentioned in DDI0516B_gic5000_r0p0_trm but not the complete definition.

  • GIC500 :: Not able to disable Affinity Routing

    I'm not able to disable the affinity routing (i.e. ARE_S and ARE_NS bits being set always). Reset value of GICD_CTLR register is 0x30.

    Actually I want to forward the interrupt from Distributor to multiple Cores but seems to use ITARGETSR, affinity…