How to identify all the coresight ROM tables present in an SoC? Can APB-AP ROM table and AHB ROM tables co-exist as part of a single ROM table in the system memory?
Hi there,
good morning.
I am using TMC as Embedded Trace Fifo and testing it for FULL condition.
Is there any way, I can stop TMC from not reading the trace data that is written in the SRAM of ETF?
So that eventually it gets full setting the FULL bit in STS…
What is SWDIO pin hardware structure? I want to know which is a push-pull or a n-channel open-drain with pull-up.
I can't find the maximum of SWD interface frequency. Please, let me know the above questions.
How does post process work for trace verification ?
The ETB/ETF sitting in the trace path may be used as a circular buffer (capture) trace sink or configured into hardware FIFO mode or software FIFo mode. So how to choose which mode need to br programme for which trace ??
HI all,
I am new to this tool. I have following queries
1. To install this, do we requires all the tools the verified in 'verify_install_cssoc.sh'
2. Becuase i dont have all the tools, i just commented the code which source 'verify_install_cssoc…
Hi i compiled the kernel code and flashed the image in ARM64 architecture juno board but the coresight devices are not being shown up in /sys/bus/coresight/devices directory. I am not getting the problem ?
In an increasingly connected world characterized by faster product-development cycles, companies continuously seek new ways to get to market sooner and to improve products throughout their life span - from production and manufacture to remote access in…
by Joseph Yiu & Ian Johnson
While the majority of Cortex-M processor-based microcontrollers are single core designs, some new microcontrollers with multiple Cortex-M processors are also available. As multi-core designs are increasing in…