• ACE protocol : Eviction and snoop request at same time

    How to handle below scenario ?

    • At time t1 let us suppose L1 data cache is evicting a line and write address is sent on write address channel by asserting AWVALID (AWREADY is high)
    • At same time t1, there is a snoop request from interconnect on snoop address…

  • Turning on MMU and caches on Cortex-A7?

    In my little program (rpi_stub) it's time to turn on MMU and caches.

    Most of it I seem to have hold of, except cache invalidations.

    In multicore situation (rpi_doesn't support yet, but maybe later), what needs to be invalidated and how?

    I understand…

  • L1 Cache Eviction Corrupting DDR on A9

    Hi All!

    I am working with a Xilinx Zynq 7000 SoC which uses the Cortex A9 as a CPU.

    I've observed a problem wherein a section of memory marked strongly-ordered and non-cacheable (0xc02) in the MMU table gets corrupted by what appears to be L1 evictions…

  • Cache in SOCs

    Dear Sir/Ma'am,

    In SOC size of interconnections between multiple processors is very small. So is it possible to have one big size central cache for all processors ignoring access time. 

    I know processors share cache memories with other processors by…

  • AMBA AXI CACHE

    i am not able to understand working of this CACHE signal pleas explain with simple example.

    thank you!

  • Cache Maintenance Transactions

    Hi,

    I am reading ACE protocol and i am confused about when to use cache maintenance transactions. On what basis should i decide when to use cache maintenance transaction and which transaction to be used?

    Can anyone please help?

  • How to handle Cache flush in ACE?

    Hi,

    I want to know which transaction should be issued by ACE interface on the channel when a flush/clean request is being processed by the cache?

    Can anyone please help.

    Regards,

    Taniya Garg

  • Introducing AMBA 5 CHI protocol enhancements: Specification now available

    In 2013 Arm announced the AMBA 5 CHI protocol to provide the performance and scale required for infrastructure applications such as networking and data center. The protocol has been highly successful and has been the foundation for Arm many core systems…

  • ARMv8-64 Cache management in a PSCI functions

    Hi everyone,

    I'm currently working on type-1 hypervisor and would like to provide support of the ARM Power State Coordination Interface. http://infocenter.arm.com/help/topic/com.arm.doc.den0022d/Power_State_Coordination_Interface_PDD_v1_1_DEN0022D…

  • Exploring the ARM CoreLink CCI-500 performance envelope - Part 1

    Introduction

    You may have noticed the ARM announcement last week of a group of Premium Mobile products (if not you can find it here ARM Sets New Standard for the Premium Mobile Experience - ARM) covering a new core processor IP, new GPU IP and a new…