• Handling invalid AXI address requests

    I'm working with the Cortex-M on digilent ARTY FPGA platform. I'm wondering how handling invalid address requests happen on a typical system. I'm guessing the address decoder in the AXI crossbar interconnect handles it somehow. Does it return an error…

  • In case of AXI4 lite protocol,what is the relation between BValid signal and Wvalid signal?

    In case of AXI4 lite protocol,whether BValid should be asserted before WVALID signal deassertion? what is the legal case?

  • AXI4-lite :Wready dependency on Awvalid and Wvalid

    In specification it is mentioned that WREADY signal can wait for AWVALID and WVALID signals.

    Does it mean that WREADY signal should be asserted only after assertion of AWVALID and WVALID signals.

    What is the relation between these signals?

    and performance…

  • needs some clarification

    Difference between axi_4 and axi4_alite?

  • Write strobe for AXI4 lite

    what are the possible values of strobe for a half word transfer in AXI4 lite? 

    Are these following values on WSTRB valid ?

    -1001

    -0101

    -1010

  • AXI-lite tlast signal missing and tready behavioral

    Dear Forum,

    Can someone please clarify my 2 questions:

    a)

    Why in AXI lite protocol there is no tlast port?

    Mainly AXI lite consists of AXI-stream protocols, but there is no tlast port in AXI lite. Can someone justify what was the reason of not including…

  • AXI transaction failure

    Hello everyone,

    I'm pretty new to axi and i still try to figure things out. I'm using Zybo device and created a custom ip with a master and a slave interfaces. I have create design as you can see in the below. Write transaction is work however, read transaction…