• Write Data Interleaving - AXI

    Note: This was originally posted on 19th March 2009 at http://forums.arm.com

    Hello,

    Can anybody help me to understand the reasoning behind write data interleaving ordering restriction imposed by AXI spec.
    [Chapter 8.5  Write data interleaving]

    "The order…

  • In AMBA AHB, is hgrnat must be low after 1st clock cycle of an ERROR response?

    Hi,

    In AMBA AHB:-

         For two clock cycle SPLIT or RETRY response, hgrant must be low after 1st clock cycle of SPLIT or RETRY response.

       q)  For two clock cycle ERROR response, is it mandatory of hgrant must be low after 1st clock…

  • AHB HREADY low not after address phase

    What would happen if HREADY will be lower not after address phase, but according to HW internal logic that wants to hold CPU for some clock cycles.

    Thanks

  • In AHB 2.0 Standard, Can I insert BUSY cycles in INCR16 burst or WRAP16 burst?

    I am a Digital Verification Design Engineer.

    Currently, I am in the process of developing an UVM Test Bench for AHB 2.0.


    I have following questions.

    1) From AHB Master side, Can BUSY cycles be inserted in middle of INCR16 burst?

    2) From AHB Master side,…

  • AMBA ATP: Gaining momentum with workload modeling

    Workload modeling utilities are a critical component of a System-on-Chip (SoC) performance analysis solution. They are as important as accurate IP models, deep debug and trace instrumentation and visualization of performance analytics.

    We recently announced…

  • STM(System Trace Macrocell)

    Can i observe the 1KB data that it is written over the STM AXI interface from STM ATB BUS ?

    what i mean is that i want to send a 1KB data from STM AXI and observe it from the STM ATB with MIPI STPv2 format.

  • AMBA

    How is it possible for AMBA bus protocol to communicate between ASB bus and APB bus,if they operate in different frequency's? ASB is high performance high frequency bus and APB is low performance low frequency bus..how that communication is happening…

  • Assertion for Multiple Transfer on APB Bus

    Hi,

       Can you please help me in writing assertions to take care on multiple transfer in APB bus?

    Thanks,

    Rakesh

  • AMBA Adaptive Traffic Profiles

    The performance requirements of computing systems have been growing rapidly, year on year. Demand is further increased by the many new performance-demanding applications that are emerging across multiple market segments, such as machine learning (ML)…

  • Project on AXI Bus.

    Hi,

    I am working on AXI bus for my college project. For my work I have to add something new in existing architecture. Can someone provide me idea for my work? 

  • does ARM v8 bus architecture & related IPs be compatible with v7 core?

    I would like to get some confirmation that if we replace A53/A72 with A7/A9 while the SoC architecture is still based on ARM v8 bus & IPs (e.g. CCI400, NIC400, TZC400, GIC500, BP141), does such design feasible and workable?